PDF MC74HC597 Data sheet ( Hoja de datos )

Número de pieza	MC74HC597
Descripción	8-Bit Serial or Parallel-Input/Serial-Output Shift Register with Input Latch
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register with Input Latch High–Performance Silicon–Gate CMOS The MC54/74HC597 is identical in pinout to the LS597. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of an 8–bit input latch which feeds parallel data to an 8–bit shift register. Data can also be loaded serially (see Function Table). The HC597 is similar in function to the HC589, which is a 3–state device. • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2 to 6 V • Low Input Current: 1 µA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 516 FETs or 129 Equivalent Gates SERIAL DATA INPUT SA 14 PARALLEL DATA INPUTS A 15 B1 C2 D3 E4 F5 G6 H7 LATCH CLOCK 12 SHIFT CLOCK 11 SERIAL SHIFT/ 13 PARALLEL LOAD RESET 10 LOGIC DIAGRAM INPUT LATCH SHIFT REGISTER SERIAL 9 QH DATA OUTPUT PIN 16 = VCC PIN 8 = GND MC54/74HC597 16 1 J SUFFIX CERAMIC PACKAGE CASE 620–10 16 1 N SUFFIX PLASTIC PACKAGE CASE 648–08 16 1 D SUFFIX SOIC PACKAGE CASE 751B–05 ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXD Ceramic Plastic SOIC PIN ASSIGNMENT B1 C2 16 VCC 15 A D3 E4 F5 14 SA 13 SERIAL SHIFT/ PARALLEL LOAD 12 LATCH CLOCK G6 H7 11 SHIFT CLOCK 10 RESET GND 8 9 QH 10/95 © Motorola, Inc. 1995 1 REV 6 1 page MC54/74HC597 LATCH CLOCK tw tr 90% 50% 10% tf SWITCHING WAVEFORMS 1/fmax VCC tw SHIFT CLOCK 50% GND VCC GND tPLH tPHL QH 90% 50% 10% tTLH tTHL Figure 1. (Serial Shift/Parallel Load = L) RESET tPHL QH tw 50% 50% SHIFT CLOCK VCC GND trec Figure 3. tPLH tPHL QH 50% Figure 2. (Serial Shift/Parallel Load = H) SERIAL SHIFT/ PARALLEL LOAD QH tw 50% tPLH 50% 50% tPHL VCC GND Figure 4. VALID VALID PARALLEL DATA A/H 50% VCC SERIAL DATA GND INPUT SA 50% VCC GND tsu th tsu th VCC VCC LATCH CLOCK 50% SHIFT CLOCK 50% GND GND Figure 5. Figure 6. SERIAL SHIFT/ PARALLEL LOAD SHIFT CLOCK 50% tsu 50% Figure 7. VCC GND VCC GND DEVICE UNDER TEST TEST POINT OUTPUT CL* * Includes all probe and jig capacitance Figure 8. Test Circuit High–Speed CMOS Logic Data DL129 — Rev 6 5 MOTOROLA 5 Page

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