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PDF ST63T156B1 Data sheet ( Hoja de datos )
| Número de pieza | ST63T156B1 | |
| Descripción | (ST63T1xx) 8-BIT HCMOS MCUs FOR TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD | |
| Fabricantes | ST Microelectronics | |
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ST63140, ST63146
ST63126, ST63156
DATA SHEET
1st Edition
OCTOBER 1993
1 page  
ST63140, ST63142
® ST63126, ST63156
8-BIT HCMOS MCUs FOR
TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD
PRELIMINARY DATA
4.5 to 6V operating Range
8MHz Maximum Clock Frequency
User Program ROM: 7948 bytes
Reserved Test ROM: 244 bytes
Data ROM:
user selectable size
Data RAM:
256 bytes
Data EEPROM:
128 bytes
40-Pin Dual in Line Plastic Package for the
ST63126, 156
28-Pin Dual in Line Plastic Package for the
ST63140, 142
Up to 18 software programmable general pur-
pose Inputs/Outputs, including 8 direct LED
driving Outputs
3 Inputs for keyboard scan (KBY0-2)
Up to 4 high voltage outputs (BSW0-3)
Two Timers each including an 8-bit counter with
a 7-bit programmable prescaler
Digital Watchdog Function
Serial Peripheral Interface (SPI) supporting
S-BUS/ I2C BUS and standard serial protocols
Up to Four 6-bit PWM D/A Converters
62.5kHz Output pin
14 bit counter for voltage synthesis tuning
(ST63156, ST63140)
AFC A/D converter with 0.5V resolution
Four interrupt vectors (IRIN/NMI, Timer 1 & 2,
VSYNC.)
On-chip clock oscillator
5 Lines by 15 Characters On-Screen Display
Generator with 128 Characters (2 banks)
All ROM types are supported by pin-to-pin
EPROM and OTP versions.
The development tool of the ST631xx microcon-
trollers consists of the ST63TVS-EMUemulation
and development system to be connected via a
standard RS232 serial line to an MS-DOS Per-
sonal Computer.
1
PDIP40
1
PDIP28
(Ordering Information at the end of the datasheet)
DEVICE SUMMARY
DEVICE
ROM
(Bytes)
TUN. I/O Pins Package
ST63126
8K FS 12 PDIP40
ST63156
8K VS 11 PDIP40
ST63140
8K VS
6 PDIP28
ST63142
8K FS
6 PDIP28
October 1993
This is Preliminary information from SGS-THOMSON. Details are subject to change without notice.
1/82
5 Page 
ST63140,142,126,156
ST631xx CORE
The Core of the ST631xx Family is implemented
independently from the I/O or memory configura-
tion. Consequently, it can be treated as an inde-
pendent central processor communicating with I/O
and memory via internal addresses, data, and con-
trol busses. The in-core communication is ar-
ranged as shown in the following block diagram
figure; the controller being externally linked to both
the reset and the oscillator, while the core is linked
to the dedicated on-chip macrocells peripherals via
the serial data bus and indirectly for interrupt pur-
poses through the control registers.
Registers
The ST631xx Family Core has six registers and
three pairs of flags available to the programmer.
They are shown in Figure 5 and are explained in
the following paragraphs together with the pro-
gram and data memory page registers.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator is addressed in the data
space as RAM location at address FFh .
Accordingly, the ST631xx instruction set can use
the accumulator as any other register of the data
space.
Figure 5. ST631xx Core Programming Model
INDEX
REGISTER
b7 X REG. POINTER b0
SHORT
b7 Y REG. POINTER b0 DIRECT
ADDRESSING
b7 V REGISTER b0 MODE
b7 W REGISTER
b0
b7 ACCUMULATOR b0
b11 PROGRAM COUNTER
b0
SIX LEVELS
STACK REGISTER
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
CZ
CZ
CZ
VA000423
Figure 4. ST631xx Core Block Diagram
RESET
0,0 1 TO 8MHz
OS Cin
OSCout
PROGRAM
ROM / EPROM
12
OPCODE
CONT ROL L ER
F LAG
VALUES
2
CONTROL
SIGNALS
I NT ERRUPTS
DATA SPACE
ADDRESS / READ LINE
DATA
RAM / EEPROM
Program Counter
and
6 LAYER STACK
A-DATA
B- DATA
FLAGS
ALU
ADDRESS
DECODER
256
DATA
ROM / EPROM
DEDICATIONS
ACCUMUL ATOR
RESULTS TO DATA SPACE ( WRITE LINE )
VR001811
7/82
®
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