PDF UDA1321 Data sheet ( Hoja de datos )

Número de pieza	UDA1321
Descripción	Universal Serial Bus USB Digital-to-Analog Converter DAC
Fabricantes	Philips
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET UDA1321 Universal Serial Bus (USB) Digital-to-Analog Converter (DAC) Preliminary speciﬁcation Supersedes data of 1998 May 12 File under Integrated Circuits, IC01 1998 Oct 06 1 page Philips Semiconductors Universal Serial Bus (USB) Digital-to-Analog Converter (DAC) BLOCK DIAGRAM handbook, full pagewidth D+ D− TC RTCB SHTCB TEST CONTROL BLOCK GP4/BCKO GP3/WSO GP2/DO GP1/DI GP0/BCKI GP5/WSI ANALOG FRONT-END USB-PROCESSOR DIGITAL I/O VSSX XTAL1 XTAL2 VDDX SAMPLE FREQUENCY GENERATOR OSC TIMING FIFO REGISTERS fs AUDIO FEATURE PROCESSING DSP fs UP-SAMPLE FILTERS 64fs VARIABLE HOLD REGISTER 128fs 3rd-ORDER NOISE SHAPER VOUTL LEFT DAC RIGHT DAC Preliminary speciﬁcation UDA1321 MICRO- CONTROLLER SCL SDA EA PSEN ALE P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 UDA1321H UDA1321T UDA1321PS VDDE VSSE VSSI VDDI VDDO VSSO VDDA VSSA VOUTR 1998 Oct 06 REFERENCE VOLTAGE Vref Fig.1 Block diagram. 5 MGM839 5 Page Philips Semiconductors Universal Serial Bus (USB) Digital-to-Analog Converter (DAC) Preliminary speciﬁcation UDA1321 The Asynchronous Digital-to-Analog Converter (ADAC) The ADAC receives USB audio information from the USB processor or from the digital I/O-bus. The ADAC is able to reconstruct the sample clock from the rate at which the audio samples arrive and handles the audio sound processing. After processing, the audio signal is up-sampled, noise-shaped and converted to analog output voltages capable of driving a line output. The ADAC consists of: • A Sample Frequency Generator (SFG) • First-In First-Out (FIFO) registers • An audio feature processing DSP • Two digital up-sample filters • A variable hold register • A digital Noise Shaper (NS) • A Filter Stream DAC (FSDAC) with integrated filter and line output drivers. THE SAMPLE FREQUENCY GENERATOR (SFG) The SFG controls the timing signals for the asynchronous digital-to-analog conversion. By means of a digital PLL, the SFG automatically recovers the applied sampling frequency and generates the accurate timing signals for the audio feature processing DSP and the up-sample ﬁlters. FIRST-IN FIRST-OUT (FIFO) REGISTERS The FIFO registers are used to store the audio samples temporarily coming from the USB processor or from the digital I/O input. The use of a FIFO register (in conjunction with the SFG) is necessary to remove all jitter present on the incoming audio signal. THE AUDIO FEATURE PROCESSING DSP A DSP processes the sound features. The control and mapping of the sound features is explained in Section “Controlling the USB Digital-to-Analog Converter (DAC)”. Depending on the sampling rate (fs) the DSP has four frequency domains in which the treble and bass are regulated (see Table 1). The domain is chosen automatically. THE UP-SAMPLE FILTERS AND VARIABLE HOLD REGISTER After the audio feature processing DSP two up-sample filters and a variable hold register increase the oversampling rate to 128fs. Table 1 Frequency domains for audio processing DOMAIN 1 2 3 4 SAMPLE FREQUENCY (kHz) 5 to 12 12 to 25 25 to 40 40 to 55 THE NOISE SHAPER A 3rd-order noise shaper converts the oversampled data to a noise-shaped bitstream for the FSDAC. The in-band quantization noise is shifted to frequencies well above the audio band. THE FILTER STREAM DAC (FSDAC) The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed because of the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. USB Digital-to-Analog Converter (DAC) descriptors In a typical USB environment the USB host has to know which kind of devices are connected. For this purpose each device contains a number of USB descriptors. These descriptors describe, from different points of view (USB configuration, USB interface and USB endpoint), the capabilities of a device. Each of them can be requested by the host. The collection of descriptors is denoted as a descriptor map. This descriptor map will be reported to the USB host during enumeration and on request. The full descriptor map is implemented in the firmware exploiting the full functionality of the UDA1321. The USB descriptors and their most important fields, in relationship to the characteristics of the UDA1321 are briefly explained below. GENERAL DESCRIPTORS The UDA1321 supports one configuration containing a control interface, an audio interface and a HID interface. The descriptor map that describes this configuration is partly fixed and partly programmable. 1998 Oct 06 11 11 Page

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