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PDF UDA1325 Data sheet ( Hoja de datos )
| Número de pieza | UDA1325 | |
| Descripción | Universal Serial Bus USB CODEC | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
DATA SHEET
UDA1325
Universal Serial Bus (USB) CODEC
Preliminary specification
File under Integrated Circuits, IC01
1999 May 10
1 page  
Philips Semiconductors
Universal Serial Bus (USB) CODEC
BLOCK DIAGRAM
Preliminary specification
UDA1325
handbook, full pagewidth
VSSX
XTAL1b
XTAL2b
VDDX
VDDA3
XTAL2a
XTAL1a
VSSA3
24 (19)
25 (20)
26 (21)
28 (22)
52 (39)
53 (40)
54 (41)
55 (42)
CLK
27
OSC
48 MHz
TIMING
OSC
ADC
ANALOG
PLL
D+
8 (9)
D−
6 (8)
ANALOG FRONT-END
USB-PROCESSOR
P0.7 to P0.0
7, 5, 3, 64,
62, 60, 58, 56
P2.0 to P2.7
14, 16, 18, 20,
22, 23, 29, 30
(10) 9
(11) 10
(12) 11
(13) 12
(23) 32
(24) 33
(29) 38
(30) 39
(33) 42
(35) 44
VDDI
VSSI
VSSE
VDDE
VDDO
VSSO
VDDA1
VSSA1
VDDA2
VSSA2
GP2/DO 63 (4)
GP3/WSO 1 (5)
GP4/BCKO 2 (6)
GP1/DI 13 (14)
GP0/BCKI 17 (16)
GP5/WSI 15 (15)
PSEN 31
DA
WS
BCK
57 (1)
59 (2)
61 (3)
EA 48
ALE 50
VINL 43 (34)
PGA
VINR 47 (36)
PGA
VRN 49 (37)
VRP 51 (38)
DIGITAL I/O
MUX
I2S-BUS
INTERFACE
DECIMATOR
FILTER
SAMPLE
FREQUENCY
GENERATOR
FIFO
AUDIO FEATURE
PROCESSING DSP
UPSAMPLE FILTERS
LEFT
Σ∆ ADC
RIGHT
Σ∆ ADC
UDA1325
VARIABLE HOLD REGISTER
3rd-ORDER NOISE SHAPER
LEFT
DAC
REFERENCE VOLTAGE
RIGHT
DAC
45, 46
n.c.
41 (32)
Vref(AD)
40 (31)
Vref(DA)
MICRO-
CONTROLLER
(17) 19 SCL
(18) 21 SDA
TEST
CONTROL
BLOCK
(7) 4 SHTCB
(26) 35 TC
(27) 36 RTCB
− (25) 34 VOUTL
+
+ (28) 37 VOUTR
−
MGM108
The pin numbers given in parenthesis refer to the SDIP42 version.
Fig.1 Block diagram (QFP64 package).
1999 May 10
5
5 Page 
Philips Semiconductors
Universal Serial Bus (USB) CODEC
Preliminary specification
UDA1325
The clock source of the analog-to-digital interface
The clock source of the ADIF is the analog PLL or the ADC oscillator. The preferred clock source can be selected.
The ADC clock used for the ADC and decimation filters is obtained by dividing the clock signal coming from the analog
PLL or from the ADC oscillator by a factor Q.
Using the analog PLL the user can select 3 basic APLL clock frequencies (see Table 1).
By connecting the appropriate crystal the user can choose any clock signal between 8.192 and 14.08 MHz via the ADC
oscillator.
Table 1 The analog PLL clock output frequencies
FCODE (1 AND 0)
00
01
10
11
APLL CLOCK
FREQUENCY (MHz)
11.2896
8.1920
12.2880
11.2896
The dividing factor Q can be selected via the microcontroller. With this dividing factor Q the user can select a range of
ADC clock signals allowing several different sample frequencies (see Table 2).
Table 2 ADC clock frequencies and sample frequencies based upon using the APLL as a clock source
APLL CLOCK
FREQUENCY (MHz)
8.1920
11.2896
12.2880
DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz)
1 4.096
32
2 2.048
16
4 1.024
8
8
0.512 (not supported)
4 (not supported)
1 5.6448
44.1
2 2.8224
22.05
4 1.4112
11.025
8 0.7056
5.5125
1 6.144
48
2 3.072
24
4 1.536
12
8 0.768
6
Table 3 ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source
OSCAD CLOCK
FREQUENCY (MHz)
fosc(1)
DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz)
Q(2) fosc/(2Q)
fosc/(256Q)(3)
Notes
1. The oscillator frequency (and therefore the crystal) of OSCAD must be between 8.192 and 14.08 MHz.
2. The Q factor can be 1, 2, 4 or 8.
3. Sample frequencies below 5 kHz and above 55 kHz are not supported.
1999 May 10
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UDA1325.PDF ] | |
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