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PDF DP8224 Data sheet ( Hoja de datos )
| Número de pieza | DP8224 | |
| Descripción | Clock Generator and Driver | |
| Fabricantes | National | |
| Logotipo |  |
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June 1986
DP8224 Clock Generator and Driver
General Description
The DP8224 is a clock generator driver contained in a stan-
dard 16-pin dual-in-line package The chip which is fabri-
cated using Schottky Bipolar technology generates clocks
and timing for the 8080A microcomputer family
Included in the DP8224 is an oscillator circuit that is con-
trolled by an external crystal which is selected by the de-
signer to meet a variety of system speed requirements Also
included in the chip are circuits that provide a status strobe
for the DP8228 or DP8238 system controllers power-on re-
set for the 8080A microprocessor and synchronization of
the READY input to the 8080A
Features
Y Crystal-controlled oscillator for stable system operation
Y Single chip clock generator and driver for 8080A micro-
processor
Y Provides status strobe for DP8228 or DP8238 system
controllers
Y Provides power-on reset for 8080A microprocessor
Y Synchronizes READY input to 8080A microprocessor
Y Provides oscillator output for synchronization of exter-
nal circuits
Y Reduces system component count
8080A Microcomputer Family Block Diagram
C1995 National Semiconductor Corporation TL F 8752
TL F 8752 – 1
RRD-B30M105 Printed in U S A
1 page  
Functional Pin Definitions
The following describes the function of all of the DP8224
input output pins Some of these descriptions reference in-
ternal circuits
INPUT SIGNALS
Crystal Connections (XTAL 1 and XTAL 2) Two inputs
that connect an external crystal to the oscillator circuit of
the DP8224 Normally a fundamental mode crystal is used
to determine the basic operating frequency of the oscillator
However overtone mode crystals may also be used The
crystal frequency is 9 times the desired microprocessor
speed (that is crystal frequency equals 1 tCY c 9) When
the crystal frequency is above 10 MHz a selected capacitor
(3 to 10 pF) may have to be connected in series with the
crystal to produce the exact desired frequency Figure A
Tank Allows the use of overtone mode crystals with the
oscillator circuit When an overtone mode crystal is used
the tank input connects to a parallel LC network that is ac
coupled to ground The formula for determining the reso-
nant frequency of this LC network is as follows
1
Fe
2q 0LC
Synchronizing (SYNC) Signal When high indicates the
beginning of a new machine cycle The 8080A microproces-
sor outputs a status word (which describes the current ma-
chine cycle) onto its data bus during the first state (SYNC
interval) of each machine cycle
Reset In (RESIN) Provides an automatic system reset and
start-up upon application of power as follows The RESIN
input which is obtained from the junction of an external RC
network that is connected between VCC and ground is rout-
ed to an internal Schmitt Trigger circuit This circuit converts
the slow transition of the power supply rise into a sharp
clean edge when its input reaches a predetermined value
When this occurs an internal D-type flip-flop is synchro-
nously reset thereby providing the RESET output signal dis-
cussed below
Logic and Connection Diagrams
For manual system reset a momentary contact switch that
provides a low (ground) when closed is also connected to
the RESIN input
Ready In (RDYIN) An asynchronous READY signal that is
re-clocked by a D-type flip-flop of the DP8224 to provide the
synchronous READY output discussed below
a5 Volts VCC supply
a12 Volts VDD supply
Ground 0 volt reference
OUTPUT SIGNALS
Oscillator (OSC) A buffered oscillator signal that can be
used for external timing purposes
w1 and w2 Clocks Two non-TTL compatible clock phases
that provide nonoverlapping timing references for internal
storage elements and logic circuits of the 8080A microproc-
essor The two clock phases are produced by an internal
clock generator that consists of a divide-by-nine counter
and the associated decode gating logic Figure B
w2 (TTL) Clock A TTL w2 clock phase that can be used for
external timing purposes
Status Strobe (STSTB) Activated (low) at the start of each
new machine cycle The STSTB signal is generated by gat-
ing a high-level SYNC input with the w1A timing signal from
the internal clock generator of the DP8224 The STSTB sig-
nal is used to clock status information into the status latch
of the DP8228 system controller and bus driver
Reset When the RESET signal is activated the content of
the program counter of the 8080A is cleared After
RESET the program will start at location 0 in memory
Ready The READY signal indicates to the 8080A that valid
memory or input data is available This signal is used to
synchronize the 8080A with slower memory or input output
devices
Dual-In-Line Package
Top View
TL F 8752 – 5
Order Number DP8224J or DP8224N
See NS Package Number
J16A or N16A
TL F 8752 – 4
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet DP8224.PDF ] | |
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