PDF ST7FLITE1xxx Data sheet ( Hoja de datos )

Número de pieza	ST7FLITE1xxx
Descripción	8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY
Fabricantes	ST Microelectronics
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ST7LITE1 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 4 TIMERS, SPI ■ Memories – 4 Kbytes single voltage extended Flash (XFlash) Program memory with read-out pro- tection, In-Circuit Programming and In-Appli- cation programming (ICP and IAP). 10K write/ erase cycles guaranteed, data retention: 20 years at 55°C. – 256 bytes RAM – 128 bytes data E2PROM with read-out protec- tion. 300K write/erase cycles guaranteed, data retention: 20 years at 55°C. ■ Clock, Reset and Supply Management – Enhanced reset system – Enhanced low voltage supervisor (LVD) for main supply and an auxiliary voltage detector (AVD) with interrupt capability for implement- ing safe power-down procedures – Clock sources: Internal 1% RC oscillator (on some devices), crystal/ceramic resonator or external clock – Internal 32-MHz input clock for Auto-reload timer – Optional x4 or x8 PLL for 4 or 8 MHz internal clock – Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow ■ I/O Ports – Up to 15 multifunctional bidirectional I/O lines – 7 high sink outputs ■ 4 Timers – Configurable watchdog timer – Two 8-bit Lite Timers with prescaler, Device Summary Features Program memory - bytes RAM (stack) - bytes Data EEPROM - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages ST7LITE10 - Lite Timer with Watchdog, Autoreload Timer, SPI, 10-bit ADC with Op-Amp Up to 8Mhz (w/ ext OSC up to 16MHz) December 2004 SO20 1 realtime base and 1 input capture – One 12-bit Auto-reload Timer with 4 PWM outputs, input capture and output compare functions ■ Communication Interface – SPI synchronous serial interface ■ Interrupt Management – 10 interrupt vectors plus TRAP and RESET – 15 external interrupt lines (on 4 vectors) ■ A/D Converter – 7 input channels – Fixed gain Op-amp – 13-bit precision for 0 to 430 mV (@ 5V VDD) – 10-bit precision for 430 mV to 5V (@ 5V VDD) ■ Instruction Set – 8-bit data manipulation – 63 basic instructions with illegal opcode de- tection – 17 main addressing modes – 8 x 8 unsigned multiply instructions ■ Development Tools – Full hardware/software development package – DM (Debug Module) ST7LITE15 ST7LITE19 4K 256 (128) - 128 Lite Timer with Watchdog, Autoreload Timer with 32-MHz input clock, SPI, 10-bit ADC with Op-Amp 2.4V to 5.5V Up to 8Mhz (w/ ext OSC up to 16MHz and int 1MHz RC 1% PLLx8/4MHz) -40°C to +85°C SO20 300” Rev. 2.0 1/131 1 1 page ST7LITE1 1 INTRODUCTION The ST7LITE1 is a member of the ST7 microcon- troller family. All ST7 devices are based on a com- mon industry-standard 8-bit core, featuring an en- hanced instruction set. The ST7LITE1 features FLASH memory with byte-by-byte In-Circuit Programming (ICP) and In- Application Programming (IAP) capability. Under software control, the ST7LITE1 device can be placed in WAIT, SLOW, or HALT mode, reduc- ing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to Figure 1. General Block Diagram software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. For easy reference, all parametric data are located in section 13 on page 91.The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM reg- isters, refer to the ST7 ICC Protocol Reference Manual. CLKIN OSC1 OSC2 VDD VSS RESET Int. 1% RC 1MHz PLL 8MHz -> 32MHz PLL x 8 or PLL X4 Ext. OSC 1MHz to 16MHz /2 LVD POWER SUPPLY Internal CLOCK CONTROL 8-BIT CORE ALU PROGRAM MEMORY (4K Bytes) RAM (256 Bytes) 12-Bit Auto-Reload TIMER 2 8-Bit LITE TIMER 2 PORT A PORT B ADC + OpAmp SPI Debug Module DATA EEPROM (128 Bytes) WATCHDOG PA7:0 (8 bits) PB6:0 (7 bits) 5/131 1 5 Page ST7LITE1 Address Block Register Label Register Name Reset Status Remarks 0037h ITC EICR 0038h MCC MCCSR 0039h Clock and RCCR 003Ah Reset SICSR 003Bh 003Ch ITC EISR 003Dh to 0048h 0049h 004Ah AWU AWUPR AWUCSR 004Bh 004Ch 004Dh 004Eh 004Fh 0050h DM3) DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L 0051h to 007Fh External Interrupt Control Register Main Clock Control/Status Register RC oscillator Control Register System Integrity Control/Status Register Reserved area (1 byte) External Interrupt Selection Register 00h 00h FFh 0000 0XX0h 0Ch R/W R/W R/W R/W R/W Reserved area (12 bytes) AWU Prescaler Register AWU Control/Status Register DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low FFh R/W 00h R/W 00h R/W 00h R/W 00h R/W 00h R/W 00h R/W 00h R/W Reserved area (47 bytes) Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the Debug Module registers, see ICC reference manual. 11/131 1 11 Page

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