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PDF SP5659KGMP1T Data sheet ( Hoja de datos )
| Número de pieza | SP5659KGMP1T | |
| Descripción | 27GHz I2C Bus Low Phase Noise Synthesiser | |
| Fabricantes | Mitel Networks | |
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Supersedes March 1996 version, DS4206-1.8
SP5659
2·7GHz I2C Bus Low Phase Noise Synthesiser
Preliminary Information
DS4296 - 2.0 June 1998
The SP5659 is a single chip frequency synthesiser designed
for tuning systems up to 2·7GHz.
The RF preamplifier drives a divide-by two prescaler which
can be disabled for applications up to 2GHz, allowing direct
interfacing with the programmable divider, resulting in a step
size equal to the comparison frequency. For applications up
to 2·7GHz the divide-by two is enabled to give a step size of
twice the comparison frequency.
The comparison frequency is obtained either from an on-
chip crystal controlled oscillator or from an external source.
The oscillator frequency FREF or the comparison frequency
FCOMP may be switched to the REF/COMP output; this feature
is ideally suited to providing the reference frequency for a
second synthesiser such as in a double conversion tuner (see
Fig. 5).
The synthesiser is controlled via an I2C bus and responds
to one of four programmable addresses which are selected by
applying a specific voltage to the Address input. This feature
enables two or more synthesisers to be used in a system.
The SP5659 contains four switching ports, P0-P3 and a
5-level ADC, the output of which can be read via the I2C bus.
The SP5659 also contains a varactor line disable and
charge pump disable facility.
FEATURES
s Complete 2·7GHz Single Chip System
s Optimised for Low Phase Noise
s Selectable 42 prescaler
s Selectable Reference Division Ratio
s Selectable Reference/Comparison Frequency Output
s Selectable Charge Pump Current
s Varactor Drive Amplifier Disable
s 5-Level ADC
s Variable I2C BUS Address for Multi-tuner Applications
CHARGE PUMP
CRYSTAL
REF/COMP
ADDRESS
SDA
SCL
PORT P3
PORT P2
1 16
2 15
3 14
4 13
SP5659
5 12
6 11
7 10
89
DRIVE
VEE
RF INPUT
RF INPUT
VCC
ADC
PORT P0
PORT P1
Fig. 1 Pin connections – top view
MP16
s ESD Protection: 4kV, Mil-Std-883C, Method 3015 (1)
s Pin Compatible with SP5658
(1) Normal ESD handling precautions should be observed.
APPLICATIONS
s Satellite TV
s High IF Cable Tuning Systems
THERMAL DATA
uJC = 41°C/W
uJA = 111°C/W
ORDERING INFORMATION
SP5659 KG/MP1S (Tubes)
SP5659 KG/MP1T (Tape and reel)
1 page  
The POR is reset to 0 when the read sequence is terminated
by a STOP command. When POR is set high (at low VCC), the
programmed information is lost and the output ports are all set
to high impedance.
Bit 2 (FL) indicates whether the device is phase locked, a
logic ‘1’ is present if the device is locked, and a logic ‘0’ if the
device is unlocked.
Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of
the ADC. The ADC can be used to feed AFC information to the
microprocessor via the I2C bus.
Additional Programmable Features
Prescaler enable
The 42 prescaler is enabled by setting bit PE in byte 4 to
a logic ‘1’. A logic ‘0’ disables the prescaler, directly passing
the RF input to the 17-bit counter. Bit PE is a static select only.
SP5659
Charge pump current
The charge pump current can be programmed by bits C1 and
C0 in data byte 5, as defined in Fig. 3, Table 7.
Test mode
The test modes are invoked by setting bit RE to logic ‘0’ and
bit RTS to logic ‘1’ within the programming data and are selected
by bits TS2, TS1 and TS0 as shown in Fig. 3, Table 6. When TS2,
TS1 and TS0 are received, the device retains previously P2, P1
and P0 data.
Reference comparison frequency output
The reference frequency FREF can be switched to the REF/
COMP output (pin 3) by setting byte 5 bit RE to logic ‘1’ and bit
RTS to logic ‘0’. The comparison frequency FCOMP can be
switched to the REF/COMP output by setting bit RE to logic ‘1’
and bit RTS to logic ‘1’. For RE set to logic ‘0’, the output is
disabled and set to a high state. RE and RTS default to logic ‘1’
during power-up, thus enabling FCOMP at the REF/COMP output.
MSB
LSB
Address
Programmable divider
Programmable divider
Control data
1
0
27
1
1000
214 213 212 211
26 25 24 23
216 215 PE R3
MA1
210
22
R2
MA0
29
21
R1
0
28
20
R0
A
A
A
A
Control data
C1 C0 RE RTS P3 P2/TS2 P1/TS1 P0/TS0 A
Table 1 Write data format (MSB transmitted first)
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Address
Status byte
1 1 0 0 0 MA1 MA0 1 A Byte 1
POR FL X X X A2 A1 A0 A Byte 2
Table 3 Read data format
A2 A1 A0 Voltage on ADC input
1 00
0 11
0 10
0 01
0 00
0·6VCC to VCC
0·45VCC to 0·6VCC
0·3VCC to 0·45VCC
0·15VCC to 0·3VCC
0V to 0·15VCC
Table 4 ADC levels
MA1 MA0 Address input voltage level
00
01
0V to 0·1VCC
Open circuit
10
0·4VCC to 0·6VCC
11
0·9VCC to VCC
Table 5 Address selection
A : Acknowledge bit
MA1, MA0
216-20
: Variable address bits (see Table 5)
: Programmable division ratio control bits
PE : Prescaler enable
R3, R2, R1, R0 : Reference division ratio select (see Table 1)
C1, C0
: Charge pump current select (see Table 7)
RE : Reference oscillator output enable
RTS
: REF/COMP select when RE = 1, Test mode enable when RE = 0 (see Table 6)
TS2, TS1, TS0 : Test mode control bits (valid when RE = 0 and RTS = 1,see Table 6)
P0 : Port P0 output state (always valid except when RE = 0 and RTS = 1 (see Table 6)
P3, P2, P1
: Ports P2, P1 and P0 output states
POR
: Power on reset indicator
FL : Phase lock flag
A2, A1, A0
: ADC data (see Table 4)
X : Don’t care
Fig. 3 Data formats
cont…
5
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SP5659
11
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