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PDF 74HC73 Data sheet ( Hoja de datos )
| Número de pieza | 74HC73 | |
| Descripción | Dual JK flip-flop with reset negative-edge trigger | |
| Fabricantes | Philips | |
| Logotipo |  |
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74HC73
Dual JK flip-flop with reset; negative-edge trigger
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC
standard no. 7A.
The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock
(nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock
transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock
and data inputs, forcing the nQ output LOW and the nQ output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
s Low-power dissipation
s Complies with JEDEC standard no. 7A
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s Multiple package options
s Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
1 page  
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 3:
Symbol
GND
1Q
1Q
1J
Pin description …continued
Pin Description
11 ground (0 V)
12 true flip-flop 1 output
13 complement flip-flop 1 output
14 synchronous J input for flip-flop 1
7. Functional description
7.1 Function table
Table 4: Function table [1]
Input
Output
Operating mode
nR
nCP
nJ
nK
nQ nQ
L X X X L H asynchronous reset
H ↓ h h q q toggle
l h L H load 0 (reset)
hl
H L load 1 (set)
l l q q hold (no change)
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW CP transition;
X = don’t care;
↓ = HIGH-to-LOW CP transition.
8. Limiting values
9397 750 13815
Product data sheet
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
−0.5 +7 V
IIK
input diode current
VI < −0.5 V or VI > VCC + 0.5 V
- ±20 mA
IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V - ±20 mA
IO output source or sink VO = −0.5 V to VCC + 0.5 V
current
- ±25 mA
ICC, IGND VCC or GND current
Tstg storage temperature
- ±50 mA
−65 +150 °C
Ptot power dissipation
DIP14 package
[1] -
750 mW
SO14, SSOP14 and
TSSOP14 packages
[2] -
500 mW
[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K.
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 21
5 Page 
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 8: Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8.
Symbol Parameter
Conditions
tsu set-up time nJ, nK to nCP
th hold time nJ, nK to nCP
fmax maximum clock frequency
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay nCP to nQ
propagation delay nCP to nQ
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
propagation delay nR to nQ, nQ
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
tTHL, tTLH
tW
output transition time
nCP clock pulse width HIGH or LOW
nR reset pulse width HIGH or LOW
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min Typ Max Unit
100 - - ns
20 - - ns
17 - - ns
3 - - ns
3 - - ns
3 - - ns
4.8 - - MHz
24 - - MHz
28 - - MHz
--
--
--
--
--
--
--
--
--
--
--
--
120 -
24 -
20 -
120 -
24 -
20 -
240 ns
48 ns
41 ns
240 ns
48 ns
41 ns
220 ns
44 ns
38 ns
110 ns
22 ns
19 ns
- ns
- ns
- ns
- ns
- ns
- ns
9397 750 13815
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 21
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet 74HC73.PDF ] | |
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