74HC4053 Datasheet PDF - Philips
Part Number | 74HC4053 | |
Description | Triple 2-channel analog multiplexer/demultiplexer | |
Manufacturers | Philips | |
Logo | ||
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Preview 1 page No Preview Available ! 74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Rev. 04 — 9 May 2006
Product data sheet
1. General description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.
The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a
common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select
inputs (Sn).
With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3.
With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3.
VCC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and E).
The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for
74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC − VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
2. Features
s Low ON resistance:
x 80 Ω (typical) at VCC − VEE = 4.5 V
x 70 Ω (typical) at VCC − VEE = 6.0 V
x 60 Ω (typical) at VCC − VEE = 9.0 V
s Logic level translation:
x To enable 5 V logic to communicate with ±5 V analog signals
s Typical ‘break before make’ built in
s Complies with JEDEC standard no. 7A
s ESD protection:
x HBM EIA/JESD22-A114-C exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V
s Multiple package options
s Specified from −40 °C to +85 °C and from −40 °C to +125 °C
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Philips Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Y
VCC
VEE
VCC
VCC
from
logic
Fig 4. Schematic diagram (one switch)
7. Pinning information
7.1 Pinning
VEE
VCC
VEE
Z
001aad544
2Y1
2Y0
3Y1
3Z
3Y0
E
VEE
GND
1
2
3
4
5
6
7
8
74HC4053
74HCT4053
16 VCC
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
9 S3
001aae127
Fig 5. Pin configuration DIP16, SO16 and
(T)SSOP16
74HC4053
74HCT4053
terminal 1
index area
2Y0 2
3Y1 3
3Z 4
3Y0 5
E6
VEE 7
GND(1)
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
001aae128
Transparent top view
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as supply
pin or input.
Fig 6. Pin configuration DHVQFN16
74HC_HCT4053_4
Product data sheet
Rev. 04 — 9 May 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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Information | Total 30 Pages | |
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