74FST3384DT Datasheet PDF - ON
Part Number | 74FST3384DT | |
Description | 10-Bit Low Power Bus Switch | |
Manufacturers | ON | |
Logo | ||
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10-Bit Low Power
Bus Switch
The ON Semiconductor 74FST3384 is a 10–bit low power bus
switch. The device is CMOS TTL compatible when operating between
4 and 5.5 Volts. The device exhibits extremely low RON and adds
nearly zero propagation delay. The device adds no noise or ground
bounce to the system.
• RON t 4 W Typical
• Less Than 0.25 ns–Max Delay Through Switch
• Nearly Zero Standby Current
• No Circuit Bounce
• Control Inputs are TTL/CMOS Compatible
• Pin–For–Pin Compatible With QS3384, FST3384, CBT3384
• All Popular Packages: SOIC–24, TSSOP–24, QSOP–24
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24
1
SO–24
DW SUFFIX
CASE 751E
MARKING
DIAGRAMS
24
FST3384
AWLYWW
1
OE1
B0
A0
A1
B1
B2
A2
A3
B3
B4
A4
GND
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
VCC
B9
A9
A8
B8
B7
A7
A6
B6
B5
A5
OE2
Figure 1. 24–Lead Pinout
TRUTH TABLE
OE1
L
L
H
H
OE2
B0–B4
B5–B9
L A0–A4
A5–A9
H
A0–A4
HIGH–Z State
L HIGH–Z State
A5–A9
H HIGH–Z State HIGH–Z State
NOTE: H = HIGH Voltage Level, L = LOW Voltage Level
Function
Connect
Connect
Connect
Disconnect
PIN NAMES
Pin
OE1, OE2
A0–A9
B0–B9
Description
Bus Switch Enable
Bus A
Bus B
24
1
TSSOP–24
DT SUFFIX
CASE 948H
24
FST
3384
ALYW
1
24
1
QSOP–24
QS SUFFIX
CASE 492B
24
FST3384
AWLYYWW
1
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
ORDERING INFORMATION
Device
Package
74FST3384DW
SO–24
74FST3384DWR2 SO–24
74FST3384DT TSSOP–24
74FST3384DTR2 TSSOP–24
74FST3384QS
QSOP–24
74FST3384QSR QSOP–24
Shipping
48 Units/Rail
2500 Units/Reel
96 Units/Rail
2500 Units/Reel
96 Units/Rail
2500 Units/Reel
© Semiconductor Components Industries, LLC, 2002
May, 2002 – Rev. 4
1
Publication Order Number:
74FST3384/D
|
|
74FST3384
AC Loading and Waveforms
FROM
OUTPUT
UNDER
TEST
VI
500 W
CL* 500 W
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*CL = 50 pF
Figure 3. AC Test Circuit
SWITCH
INPUT
10 %
tPLH
tf = 2.5 nS
90 %
1.5 V
90 %
1.5 V
OUTPUT
1.5 V
tf = 2.5 nS
3.0 V
10 %
GND
tPLH
VOH
1.5 V
VOL
Figure 4. Propagation Delays
ENABLE
INPUT
tf = 2.5 nS
90 %
1.5 V
tPZL
OUTPUT
tPZH
OUTPUT
10 % 10 %
1.5 V
1.5 V
tf = 2.5 nS
90 % 3.0 V
1.5 V
GND
tPZL
VOL + 0.3 V
VOL
tPHZL
VOH
VOH – 0.3 V
Figure 5. Enable/Disable Delays
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Information | Total 8 Pages | |
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