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PDF 74FST3251D Data sheet ( Hoja de datos )
| Número de pieza | 74FST3251D | |
| Descripción | 8:1 Multiplexer/Demultiplexer Bus Switch | |
| Fabricantes | ON | |
| Logotipo |  |
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74FST3251
8:1 Multiplexer/
Demultiplexer Bus Switch
The ON Semiconductor 74FST3251 is an 8:1, high performance
multiplexer/demultiplexer bus switch. The device is CMOS TTL
compatible when operating between 4 and 5.5 Volts. The device
exhibits extremely low RON and adds nearly zero propagation delay.
The device adds no noise or ground bounce to the system.
• RON t 4 W Typical
• Less Than 0.25 ns–Max Delay Through Switch
• Nearly Zero Standby Current
• No Circuit Bounce
• Control Inputs are TTL/CMOS Compatible
• All Popular Packages: QSOP–16, TSSOP–16, SOIC–16
B4 1
B3 2
16 VCC
15 B5
B2 3
B1 4
14 B6
13 B7
A5
12 B8
NC 6
11 S0
OE 7
10 S1
GND
8
9 S2
QSOP/SSOP/TSSOP
TOP VIEW
Inputs
OE S2 S1 S0
Function
L L L L A Port = B1 Port
L L L H A Port = B2 Port
L L H L A Port = B3 Port
L L H H A Port = B4 Port
L H L L A Port = B5 Port
L H L H A Port = B6 Port
L H H L A Port = B7 Port
L H H H A Port = B8 Port
HXXX
Disconnect
NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care
© Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 1
1
http://onsemi.com
MARKING
DIAGRAMS
16
16
1
SO–16
D SUFFIX
CASE 751B
FST3251
AWLYWW
1
16
1
TSSOP–16
DT SUFFIX
CASE 948F
16
FST
3251
ALYW
1
16
16
1
QSOP–16
QS SUFFIX
CASE 492
S3251
ALYW
1
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
PIN NAMES
Pin
OE1, OE2
S0, S1
A
B1, B2, B3, B4
Description
Bus Switch Enables
Select Inputs
Bus A
Bus B
ORDERING INFORMATION
Device
Package
74FST3251D
SO–16
74FST3251DR2
SO–16
74FST3251DT TSSOP–16
74FST3251DTR2 TSSOP–16
74FST3251QS
QSOP–16
74FST3251QSR QSOP–16
Shipping
48 Units/Rail
2500 Units/Reel
96 Units/Rail
2500 Units/Reel
96 Units/Rail
2500 Units/Reel
Publication Order Number:
74FST3251/D
1 page  
74FST3251
AC Loading and Waveforms
FROM
OUTPUT
UNDER
TEST
VI
500 W
500 W
CL*
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*CL = 50 pF
Figure 2. AC Test Circuit
SWITCH
INPUT
10 %
tPLH
tf = 2.5 nS
90 %
1.5 V
90 %
1.5 V
OUTPUT
1.5 V
tf = 2.5 nS
3.0 V
10 %
GND
tPLH
VOH
1.5 V
VOL
Figure 3. Propagation Delays
ENABLE
INPUT
tf = 2.5 nS
90 %
1.5 V
tPZL
OUTPUT
tPZH
OUTPUT
10 % 10 %
1.5 V
1.5 V
tf = 2.5 nS
90 % 3.0 V
1.5 V
GND
tPZL
VOL + 0.3 V
VOL
tPHZL
VOH
VOH – 0.3 V
Figure 4. Enable/Disable Delays
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74FST3251D.PDF ] | |
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