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PDF 74F401PC Data sheet ( Hoja de datos )

Número de pieza 74F401PC
Descripción CRC Generator/Checker
Fabricantes Fairchild 
Logotipo Fairchild Logotipo



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No Preview Available ! 74F401PC Hoja de datos, Descripción, Manual

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April 1988
Revised August 1999
74F401
CRC Generator/Checker
General Description
The 74F401 Cycle Redundancy Check (CRC) Generator/
Checker provides an advanced tool for implementing the
most widely used error detection scheme in serial digital
data handling systems. A 3-bit control input selects one-of-
eight generator polynomials. The list of polynomials
includes CRC-16 and CRC-CCITT as well as their recipro-
cals (reverse polynomials). Automatic right justification is
incorporated for polynomials of degree less than 16. Sepa-
rate clear and preset inputs are provided for floppy disk
and other applications. The Error output indicates whether
or not a transmission error has occurred. Another control
input inhibits feedback during check word transmission.
The 74F401 is fully compatible with all TTL families.
Features
s Eight selectable polynomials
s Error indicator
s Separate preset and clear controls
s Automatic right justification
s Fully compatible with all TTL logic families
s 14-pin package
s 9401 equivalent
s Typical applications:
Floppy and other disk storage systems
Digital cassette and cartridge systems
Data communication systems
Ordering Code:
Order Number Package Number
Package Description
74F401SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F401PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS009534
www.fairchildsemi.com

1 page




74F401PC pdf
AC Electrical Characteristics
Symbol
Parameter
fMAX
tPLH
tPHL
tPHL
tPLH
tPHL
tPLH
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay
CP to Q
Propagation Delay
MR to Q
Propagation Delay
P to Q
Propagation Delay
MR to ER
Propagation Delay
P to ER
Propagation Delay
CP to ER
AC Operating Requirements
Symbol
Parameter
tS(H)
tS(L)
tS(H)
tS(L)
tH(H)
tH(L)
tW(L)
tW(H)
tW(L)
tW(H)
tREC
tREC
Set-up Time, HIGH or LOW
D to CP
Set-up Time, HIGH or LOW
CWE to CP
Hold Time, HIGH or LOW
D and CWE to CP
P Pulse Width, LOW
Clock Pulse Width,
HIGH or LOW
MR Pulse Width, HIGH
Recovery Time
MR to CP
Recovery Time
P to CP
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ Max
100
4.5 11.5
4.0 10.0
3.0 7.5
3.0 8.5
3.5 11.0
3.0 8.5
5.0 13.0
4.5 11.5
TA = 0°C to +70°C
VCC = +5.0V
CL = 50 pF
Min Max
85
4.5 13.5
4.0 11.0
3.0 8.0
3.0 9.5
3.5 12.0
3.0 10.0
5.0 14.5
4.5 12.5
Units
MHz
ns
ns
ns
ns
ns
ns
TA = +25°C
VCC = +5.0V
Min Max
5.0
5.0
4.0
4.0
2.0
2.0
7.0
5.0
5.0
5.0
4.0
2.0
TA = 0°C to +70°C
VCC = +5.0V
Min Max
5.5
5.5
4.5
4.5
2.0
2.0
8.0
6.0
6.0
5.5
4.5
2.0
Units
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com

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