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PDF 74F350 Data sheet ( Hoja de datos )
| Número de pieza | 74F350 | |
| Descripción | 4-bit shifter | |
| Fabricantes | Philips | |
| Logotipo |  |
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Philips Semiconductors FAST Products
4-bit shifter
Product specification
74F350
FEATURES
• Shifts 4 bits of data to 0, 1, 2, 3 places under control of two
select lines
• 3-State outputs for bus organized systems
DESCRIPTION
The 74F350 is a combination logic circuit that shifts a 4-bit word
from 0 to 3 places. No clocking is required as with shift registers.
The 74F350 can be used to shift any number of bits any number of
places up or down by suitable interconnection. Shifting can be:
1. Logical — with logic zeros filled in at either end of the shifting
field.
2. Arithmetic — where the sign bit is extended during a shift down.
3. End around — where the data word forms a continuous loop.
The 3-State outputs are useful for bus interface applications or
expansion to a larger number of shift positions in end around
shifting. The active Low Output Enable (OE) controls the state of the
outputs. The outputs are in the high impedance “off” state when OE
is High, and they are active when OE is Low.
PIN CONFIGURATION
I–3 1
I–2 2
I–1 3
I0 4
I1 5
I2 6
I3 7
GND 8
16 VCC
15 Y0
14 Y1
13 OE
12 Y2
11 Y3
10 S0
9 S1
SF00205
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F350N
16-pin plastic SO
N74F350D
TYPE
74F350
TYPICAL PROPAGATION DELAY
5.2ns
TYPICAL SUPPLY CURRENT (TOTAL)
24mA
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
I–n, In
Data inputs
1.0/2.0
S0, S1
Select inputs (active Low)
1.0/2.0
OE Output Enable input (active Low)
1.0/2.0
Y0 – Y3
Data outputs
150/40
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
LOAD VALUE HIGH/LOW
20µA/1.2mA
20µA/1.2mA
20µA/1.2mA
3.0mA/24mA
1234567
I–3 I–2 I–1 I0 I1 I2 I3
9 S1
10 S0
13 OE
Y0 Y1 Y2 Y3
VCC = Pin 16
GND = Pin 8
15 14 12 11
SF00206
D MUX
10
9
0
1
G
0
3
[SHIFTER]
13 EN
≥1
10 3
1 Z10 11 2
12 1
2
13
Z11
0
≥1
3
11
Z12 12
3
2
13 1
4
14
Z13
0
≥1
5
12
Z14 13
3
2
14 1
6
15
Z15
0
≥1
7
13
Z16 14
3
2
15 1
16 0
15
14
12
11
SF00207
March 20, 1989
1 853–0368 96093
1 page  
Philips Semiconductors FAST Products
4-bit shifter
Product specification
74F350
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
MIN TYP2 MAX
UNIT
VOH
VOL
VIK
II
IIH
IIL
IOZH
High-level output voltage
Low-level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Off-state output current,
High-level voltage applied
VCC = MIN, VIL = MAX ±10%VCC
2.4
VIH = MIN, IOH = MAX ±5%VCC
2.7
3.4
VCC = MIN, VIL = MAX ±10%VCC
0.35 0.50
VIH = MIN, IOL = MAX ±5%VCC
0.35 0.50
VCC = MIN, II = IIK
–0.73 –1.2
VCC = MAX, VI = 7.0V
100
VCC = MAX, VI = 2.7V
20
VCC = MAX, VI = 0.5V
–1.2
VCC = MAX, VO = 2.7V
50
V
V
V
µA
µA
mA
µA
IOZL
Off-state output current,
Low-level voltage applied
VCC = MAX, VO = 0.5V
–50 µA
IOS Short-circuit output current3
VCC = MAX
–60
–150
mA
ICCH
22 35
mA
ICC Supply current (total)
ICCL
VCC = MAX
26 41
mA
ICCZ
26 42
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation delay
In to Yn
Propagation delay
Sn to Yn
Output Enable time to
High or Low level
Output Disable time to
High or Low level
TEST
CONDITION
Waveform 1
Waveform 1
Waveform 2
Waveform 3
Waveform 2
Waveform 3
LIMITS
VCC = +5.0V
Tamb = +25°C
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500Ω
MIN TYP MAX
MIN
MAX
3.0 4.5 6.0
2.5 4.0 5.5
3.0
2.5
7.0
6.5
4.0 7.8 10.0
3.0 6.5 8.5
4.0
3.0
11.0
9.5
2.5 5.0 7.0
4.0 7.0 9.0
2.5
4.0
8.0
10.0
2.0 3.9 5.5
2.0 4.0 5.5
2.0
2.0
6.5
6.5
UNIT
ns
ns
ns
ns
March 20, 1989
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74F350.PDF ] | |
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