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Número de pieza | 74VHCT373A | |
Descripción | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING | |
Fabricantes | STMicroelectronics | |
Logotipo | ||
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No Preview Available ! ® 74VHCT373A
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.9V (Max.)
DESCRIPTION
The 74VHCT373A is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHCT373AM
74VHCT373AT
(OE).
While the LE input is held at a high level, the Q
outputs will follow the data inputs precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
November 1999
1/10
1 page 74VHCT373A
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
Value
Un it
TA = 25 oC
-40 to 85 oC
Min. Typ . Max. Min . Max.
CIN Input Capacitance
4 10
10 pF
COUT Output Capacitance
9 pF
CPD Power Dissipation
Capacitance (note 1)
14 pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8 (per Latch)
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
Test Conditions
V CC
( V)
Value
TA = 25 oC
Min. Typ. Max.
-40 to 85 oC
Min . Max.
Un it
VOLP Dynamic Low Voltage
VOLV Quiet Output (note 1, 2)
5.0
0.6 0.9
-0.9 -0.6
VIHD Dynamic High Voltage
Input (note 1, 3)
5.0
CL = 50 pF
2.0
V
VILD Dynamic Low Voltage
Input (note 1, 3)
5.0
0.8
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n -1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
TEST CIRCUIT
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ orequivalent
RT = ZOUT of pulse generator (typically 50Ω)
SW IT CH
Open
VCC
GND
5/10
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet 74VHCT373A.PDF ] |
Número de pieza | Descripción | Fabricantes |
74VHCT373A | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING | STMicroelectronics |
74VHCT373A | Octal D-Type Latch with 3-STATE Outputs | Fairchild Semiconductor |
74VHCT373AM | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING | STMicroelectronics |
74VHCT373AM | Octal D-Type Latch with 3-STATE Outputs | Fairchild Semiconductor |
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