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PDF 74VHCT126AM Data sheet ( Hoja de datos )
| Número de pieza | 74VHCT126AM | |
| Descripción | QUAD BUS BUFFERS 3-STATE | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74VHCT126A
QUAD BUS BUFFERS (3-STATE)
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 126
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.8V (Max.)
DESCRIPTION
The 74VHCT126A is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
PRELIMINARY DATA
SOP
TSSOP
PACKAGE
SOP
TSSOP
ORDER CODES
T UB E
T&R
74VHCT126AM 74VHCT126AMTR
74VHCT126ATTR
This device requires the 3-STATE control input G
to be set low to place the output into the high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
March 2000
1/8
1 page  
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74VHCT126A
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
5/8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74VHCT126AM.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74VHCT126A | QUAD BUS BUFFERS 3-STATE | STMicroelectronics |
| 74VHCT126AM | QUAD BUS BUFFERS 3-STATE | STMicroelectronics |
| 74VHCT126AMTR | QUAD BUS BUFFERS 3-STATE | STMicroelectronics |
| 74VHCT126ATTR | QUAD BUS BUFFERS 3-STATE | STMicroelectronics |
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