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PDF 74VHC240 Data sheet ( Hoja de datos )
| Número de pieza | 74VHC240 | |
| Descripción | OCTAL BUS BUFFER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74VHC240
OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (INVERTED)
s HIGH SPEED: tPD = 3.6ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
SOP
TSSOP
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
)s OPERATING VOLTAGE RANGE:
t(sVCC(OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
uc74 SERIES 240
ds IMPROVED LATCH-UP IMMUNITY
ros LOW NOISE: VOLP = 0.9V (MAX.)
PDESCRIPTION
teThe 74VHC240 is an advanced high-speed
leCMOS OCTAL BUS BUFFER (3-STATE)
ofabricated with sub-micron silicon gate and
sdouble-layer metal wiring C2MOS technology.
bG output enable governs four BUS BUFFERs.
OThis device is designed to be used with 3 state
-memory address drivers, etc.
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHC240MTR
74VHC240TTR
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Obsolete Product(s)Figure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 5
1/12
1 page  
74VHC240
Table 9: Dynamic Switching Characteristics
Test Condition
Value
Symbol
Parameter
VOLP
VOLV
VIHD
VILD
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
VCC
(V)
5.0
5.0
5.0
CL = 50 pF
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
0.6 0.9
-0.9 -0.6
V
3.5 V
1.5 V
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
)Figure 3: Test Circuit
roduct(s) - Obsolete Product(stPLH,tPHL
PtPZL, tPLZ
tetPZH, tPHZ
TEST
oleCL =15/ 50pF or equivalent (includes jig and probe capacitance)
sRL = R1 = 1KΩ or equivalent
ObRT = ZOUT of pulse generator (typically 50Ω)
SWITCH
Open
VCC
GND
5/12
5 Page 
Table 10: Revision History
Date
12-Nov-2004
Revision
5
Description of Changes
Order Codes Revision - pag. 1.
74VHC240
Obsolete Product(s) - Obsolete Product(s)
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 74VHC240.PDF ] | |
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