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PDF 74VHC125 Data sheet ( Hoja de datos )
| Número de pieza | 74VHC125 | |
| Descripción | Quad Buffer with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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74VHC125
Quad Buffer with 3-STATE Outputs
December 2007
Features
■ High Speed: tPD = 3.8ns (Typ.) at VCC = 5V
■ Lower power dissipation: ICC = 4 µA (Max.) at
TA = 25°C
■ High noise immunity: VNIH = VNIL = 28% VCC (Min.)
■ Power down protection is provided on all inputs
■ Low noise: VOLP = 0.8V (Max.)
■ Pin and function compatible with 74HC125
General Description
The VHC125 contains four independent non-inverting
buffers with 3-STATE outputs. It is an advanced high-
speed CMOS device fabricated with silicon gate CMOS
technology and achieves the high-speed operation simi-
lar to equivalent Bipolar Schottky TTL while maintaining
the CMOS low power dissipation.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Order Number
74VHC125M
74VHC125SJ
74VHC125MTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1993 Fairchild Semiconductor Corporation
74VHC125 Rev. 1.4.0
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
tPLH, tPHL
Parameter
Propagation Delay
Time
tPZL, tPZH 3-STATE Output
Enable Time
tPLZ, tPHZ 3-STATE Output
Disable Time
tOSLH, tOSHL Output to Output
Skew
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
Conditions
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
RL = 1kΩ CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
RL = 1kΩ CL = 50pF
CL = 50pF
(3) CL = 50pF
CL = 50pF
VCC = Open
VCC = 5.0V
(4)
TA = 25°C
Min. Typ. Max.
5.6 8.0
8.1 11.5
3.8 5.5
5.3 7.5
5.4 8.0
7.9 11.5
3.6 5.1
5.1 7.1
9.5 13.2
6.1 8.8
1.5
1.0
4 10
6
14
TA = –40°C
to +85°C
Min. Max.
1.0 9.5
1.0 13.0
1.0 6.5
1.0 8.5
1.0 9.5
1.0 13.0
1.0 6.0
1.0 8.0
1.0 15.0
1.0 10.0
1.5
1.0
10
Units
ns
ns
ns
ns
ns
ns
pF
pF
pF
Notes:
3. Parameter guaranteed by design. tOSLH = |tPLHmax – tPLHmin|; tOSHL = |tPHLmax – tPHLmin|.
4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (Opr.) = CPD • VCC • fIN + ICC / 4 (per bit).
©1993 Fairchild Semiconductor Corporation
74VHC125 Rev. 1.4.0
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74VHC125.PDF ] | |
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