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PDF 74VCX32500 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX32500 | |
| Descripción | Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
March 2001
Revised August 2003
74VCX32500
Low Voltage 36-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32500 is an 36-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a high-
impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
The VCX32500 is designed for low voltage (1.4V to 3.6V)
VCC applications with I/O capability up to 3.6V.
The 74VCX32500 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.4V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (A to B, B to A)
2.9 ns max for 3.0V to 3.6V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latchup performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model >200V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OEBA should be tied to VCC through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistors; the minimum value of
the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX32500G
(Note 2)(Note 3)
BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 2: Ordering Code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2003 Fairchild Semiconductor Corporation DS500403
www.fairchildsemi.com
1 page  
DC Electrical Characteristics (Continued)
Symbol
Parameter
VOL LOW Level Output Voltage
II Input Leakage Current
IOZ 3-STATE Output Leakage
IOFF Power Off Leakage Current
ICC Quiescent Supply Current
∆ICC
Increase in ICC per Input
Note 10: Outputs disabled or 3-STATE only.
Conditions
IOL = 100 µA
IOL = 12 mA
IOL = 18 mA
IOL = 24 mA
IOL = 100 µA
IOL = 12 mA
IOL = 18 mA
IOL = 100 µA
IOL = 6 mA
IOL = 100 µA
IOL = 2 mA
0V ≤ VI ≤ 3.6V
0V ≤ VO ≤ 3.6V
VI = VIH or VIL
0V ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
VCC ≤ (VI, VO) ≤ 3.6V (Note 10)
VIH = VCC − 0.6V
VCC
(V)
2.7 - 3.6
2.7
3.0
3.0
2.3 - 2.7
2.3
2.3
1.65 - 2.3
1.65
1.4 - 1.6
1.4
1.4 - 3.6
1.4 - 3.6
0
1.4 - 3.6
1.4 - 3.6
2.7 - 3.6
Min
AC Electrical Characteristics (Note 11)
Symbol
Parameter
fMAX
Setup Time
Conditions
CL = 30 pF
tPHL Propagation Delay
tPLH Bus-to-Bus
tPHL Propagation Delay
tPLH Clock-to-Bus
CL = 15 pF
CL = 30 pF, RL = 500Ω
CL = 15 pF, RL = 2kΩ
CL = 30 pF, RL = 500Ω
CL = 15 pF, RL = 500Ω
VCC
(V)
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
TA = −40°C to +85°C
Min Max
250
200
100
80.0
0.6 2.7
0.8 3.5
1.5 7.0
1.0 14.0
0.6 4.2
0.8 5.3
1.5 9.8
1.0 19.6
tPHL Propagation Delay
tPLH LE-to-Bus
tPZL
tPZH
Output Enable Time
CL = 30 pF, RL = 500Ω
CL = 15 pF, RL = 500Ω
CL = 30 pF, RL = 500Ω
CL = 15 pF, RL = 2kΩ
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
0.6
0.8
1.5
1.0
0.6
0.8
1.5
1.0
3.8
4.9
9.8
19.6
3.8
4.9
9.8
19.6
tPLZ
tPHZ
Output Disable Time
CL = 30 pF, RL = 500Ω
CL = 15 pF, RL = 2kΩ
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
0.6
0.8
1.5
1.0
3.7
4.2
7.6
15.2
Max
0.2
0.4
0.4
0.55
0.2
0.4
0.6
0.2
0.3
0.2
0.35
±5.0
±10.0
10.0
40.0
±40.0
750
Units
V
µA
µA
µA
µA
µA
Units
Figure
Number
MHz
Figures 1,
2
ns
Figures 7,
8
Figures 1,
2
ns
Figures 7,
8
Figures 1,
2
ns
Figures 7,
8
Figures 1,
3, 4
ns
Figures 7,
9, 10
Figures 1,
3, 4
ns
Figures 7,
9, 10
5 www.fairchildsemi.com
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74VCX32500.PDF ] | |
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