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PDF 74VCX16835 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX16835 | |
| Descripción | Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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October 1998
Revised April 2000
74VCX16835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (In) to Ouputs (On) on a
Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The 74VCX16835 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74VCX16835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s Compatible with PC100 DIMM module specifications
s 1.65V–3.6V VCC specifications provided
s 3.6V tolerant inputs and outputs
s tPD (CP to On)
4.2ns max for 3.0V to 3.6V VCC
5.2ns max for 2.3V to 2.7V VCC
9.2ns max for 1.65V to 1.95V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24mA @ 3.0V
±18mA @ 2.3V
±6mA @ 1.65V
s Latchup performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC (OE to GND) through a pulldown resistor;
the minimum value of the resistor is determined by the current sourcing
capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16835MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS500173
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 10)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.5 ± 0.2V
VCC = 1.8 ± 0.15V
Units
Min Max Min Max Min Max
fMAX
Maximum Clock Frequency
250
200
100 MHz
tPHL,
tPLH
Propagation Delay
Bus to Bus
0.6 3.3 0.8 4.2 1.5 8.4 ns
tPHL,
tPLH
Propagation Delay
Clock to Bus
1.4 4.2 1.5 5.2 2.0 9.2 ns
tPHL,
tPLH
Propagation Delay
LE to Bus
0.6 3.8 0.8 4.9 1.5 9.8 ns
tPZL, tPZH Output Enable Time
0.6 3.8 0.8 4.9 1.5 9.8 ns
tPLZ, tPHZ Output Disable Time
0.6 3.9 0.8 4.5 1.5 7.6 ns
tS Setup Time
1.5 1.5 2.5
ns
tH Hold Time
0.7 0.7 1.0
ns
tW Pulse Width
1.5 1.5 4.0
ns
tOSHL
tOSLH
Output to Output Skew
(Note 11)
0.5 0.5 0.75 ns
Note 10: For CL=50pF, add approximately 300ps to the AC maximum specification.
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
AC Electrical Characteristics Over Load (Note 12)
TA = −0°C to +85°C, RL = 500Ω VCC = 3.3V ± 0.15V
Symbol
Parameter
CL = 0 pF
CL = 50 pF
Min Max Min Max
tPHL, tPLH Prop Delay Bus to Bus
0.7 2.1 1.0 3.6
tPHL, tPLH Prop Delay Clock to Bus
1.5 3.0 1.7 4.5
tPHL, tPLH Prop Delay LE to Bus
0.7 2.6 1.0 4.1
tPZL, tPZH Output Enable Time
0.7 2.6 1.0 4.1
tPLZ, tPHZ Output Disable Time
0.7 2.7 1.0 4.2
tPHL, tPLH SSO Prop Delay Clock to Bus (Note 13)
1.5 3.3
tS Setup Time
1.5 1.5
tH Hold Time
0.7 0.7
Note 12: This parameter is guaranteed by characterization but not tested.
Note 13: SSO = Simultaneous Switching Output. Any output combination of LOW-to-HIGH and/or HIGH-to-LOW transition.
Units
ns
ns
ns
ns
ns
ns
ns
ns
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
VOHV
Quiet Output Dynamic Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
VCC
TA=+25°C
Units
(V) Typical
1.8 0.35
2.5 0.7
V
3.3 0.9
1.8 −0.35
2.5 −0.7
V
3.3 −0.9
1.8 1.3
2.5 1.7
V
3.3 2.0
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74VCX16835.PDF ] | |
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