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PDF 74VCX16827 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX16827 | |
| Descripción | Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1998
Revised October 2002
74VCX16827
Low Voltage 20-Bit Buffer/Line Driver with
3.6V Tolerant Inputs and Outputs
General Description
The VCX16827 contains twenty non-inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver carrying parity. The device is byte controlled. Each
byte has NOR output enables for maximum control flexibil-
ity.
The 74VCX16827 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74VCX16827 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.2V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
2.5 ns max for 3.0V to 3.6V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16827MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
I0–I19
O0–O19
Output Enable Input (Active LOW)
Inputs
Outputs
© 2002 Fairchild Semiconductor Corporation DS500131
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 6)
Symbol
Parameter
Conditions
VCC
TA = −40°C to +85°C
Units
Figure
(V) Min Max
Number
tPHL,
tPLH
Propagation Delay
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
0.8
2.5
2.5 ± 0.2
1.0
3.0
Figures
1, 2
1.8 ± 0.15
1.5
6.0
ns
CL = 15 pF, RL = 2kΩ
1.5 ± 0.1
1.2
1.0
1.5
12.0
30
Figures
5, 6
tPZL,
tPZH
Output Enable Time
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
0.8
3.8
2.5 ± 0.2
1.0
4.9
Figures
1, 3, 4
1.8 ± 0.15
1.5
9.8
ns
CL = 15 pF, RL = 2kΩ
1.5 ± 0.1
1.2
1.0
19.6
49
Figures
5, 7, 8
tPLZ,
tPHZ
Output Disable Time
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
0.8
3.7
2.5 ± 0.2
1.0
4.2
Figures
1, 3, 4
1.8 ± 0.15
1.5
7.6
ns
CL = 15 pF, RL = 2kΩ
1.5 ± 0.1
1.2
1.0
15.2
38
Figures
5, 7, 8
tOSHL
tOSLH
Output to Output Skew
(Note 7)
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
0.5
0.5
0.75 ns
CL = 15 pF, RL = 2kΩ
1.5 ± 0.1
1.2
1.5
1.5
Note 6: For CL = 50 PF, add approximately 300 ps to the AC maximum specification.
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
VOHV
Quiet Output Dynamic Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
VCC
TA = +25°C
Units
(V) Typical
1.8 0.25
2.5 0.6
V
3.3 0.8
1.8 −0.25
2.5 −0.6
V
3.3 −0.8
1.8 1.5
2.5 1.9
V
3.3 2.2
Capacitance
Symbol
Parameter
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = 1.8, 2.5V or 3.3V, VI = 0V or VCC
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz,
VCC = 1.8V, 2.5V or 3.3V
TA = +25°C
Typical
6
7
20
Units
pF
pF
pF
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74VCX16827.PDF ] | |
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