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PDF 74VCX162838 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX162838 | |
| Descripción | Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1997
Revised July 2000
74VCX162838
Low Voltage 16-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in the Outputs
General Description
Features
The VCX162838 contains sixteen non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CP) sig-
nals. The device operates in a 16-bit word wide mode. All
outputs can be placed into 3-State through the use of the
OE pin. These devices are ideally suited for buffered or
registered 168 pin and 200 pin SDRAM DIMM memory
modules.
The 74VCX162838 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The VCX162838 is also designed with 26Ω series resistors
in the outputs. This design reduces line noise in applica-
tions such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
s Compatible with PC100 and PC133 DIMM module
specifications
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26Ω series resistors in the outputs
s tPD (CP to On)
3.9 ns max for 3.0V to 3.6V VCC
5.4 ns max for 2.3V to 2.7V VCC
9.8 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
The 74VCX162838 is fabricated with an advanced CMOS
±12 mA @ 3.0V VCC
technology to achieve high speed
ing low CMOS power dissipation.
operation
while
maintawinw-w.DataSheet4±U8.comm A
@ 2.3V VCC
±3 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor. The minimum
value of the resistor is determined by the current -sourcing capability of the
driver.
Ordering Code:
Ordering Code Package Number
Package Descriptions
74VCX162838MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
I0–I15
O0–O15
CP
REGE
Description
Output Enable Input (Active LOW)
Inputs
Outputs
Clock Pulse Input
Register Enable Input
© 2000 Fairchild Semiconductor Corporation DS500045
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 8)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.5V ± 0.2V
VCC = 1.8V
Units
Min Max Min Max Min Max
fMAX
Maximum Clock Frequency
250
200
100 MHz
tPHL, tPLH Prop Delay In to On (REGE = 0)
0.8 3.5 1.0 4.9 1.5 9.8 ns
tPHL, tPLH Prop Delay CP to On (REGE = 1)
0.8 3.9 1.0 5.4 1.5 9.8 ns
tPHL, tPLH Prop Delay REGE to On
0.8 3.9 1.0 5.4 1.5 9.8 ns
tPZL, tPZH Output Enable Time
0.8 4.0 1.0 5.7 1.5 9.8 ns
tPLZ, tPHZ Output Disable Time
0.8 4.1 1.0 4.6 1.5 8.3 ns
tS Setup Time
1.0 1.0 2.5
ns
tH Hold Time
0.7 0.7 1.0
ns
tW Pulse Width
1.5 1.5 4.0
ns
tOSHL
tOSLH
Output to Output Skew (Note 9)
0.5 0.5 0.75 ns
Note 8: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Extended AC Electrical Characteristics (Note 10)
Symbol
Parameter
tPHL, tPLH Prop Delay In to On (REGE = 0)
tPHL, tPLH Prop Delay CP to On (REGE = 1)
tPHL, tPLH Prop Delay REGE to On
tPZL, tPZH Output Enable Time
tPLZ, tPHZ Output Disable Time
tS Setup Time
tH Hold Time
Note 10: This parameter is guaranteed by characterization but not tested.
TA = −0°C to +85°C, RL = 500Ω VCC = 3.3V ± 0.3V
CL = 50 pF
Min Max
1.0 3.8
1.4 4.2
1.0 4.2
1.0 4.3
1.0 4.4
1.0
0.7
Units
ns
ns
ns
ns
ns
ns
ns
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
VOHV
Quiet Output Dynamic Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
VCC TA = +25°C Units
(V) Typical
1.8 0.15
2.5 0.25
V
3.3 0.35
1.8 −0.15
2.5 −0.25
V
3.3 −0.35
1.8 1.55
2.5 2.05
V
3.3 2.65
Capacitance
Symbol
Parameter
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
TA = +25°C
Typical
VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
VI =0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V
6
7
20
Units
pF
pF
pF
5 www.fairchildsemi.com
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