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PDF 74LVX08 Data sheet ( Hoja de datos )
| Número de pieza | 74LVX08 | |
| Descripción | Low Voltage Quad 2-Input AND Gate | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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June 2014
74LVX08
Low Voltage Quad 2-Input AND Gate
Features
• Input Voltage Level Translation from 5 V to 3 V
• Ideal for Low-power / Low-Noise 3.3 V Applications
• Guaranteed Simultaneous Switching Noise Level and
Dynamic threshold Performance
Description
The LVX08 contains four 2-input AND gates. The inputs
tolerate voltages up to 7 V allowing the interface of 5 V
systems to 3 V systems.
Ordering Information
Part Number Top Mark Package Packing Method
Packing Description
74LVX08M
LVX08 SOIC 14L
Rail
14-Lead Small Outline Integrated Circuit, JEDEC
MS-012, 0.150 inch Narrow
74LVX08MX
LVX08
SOIC 14L
Tape and Reel
14-Lead Small Outline Integrated Circuit, JEDEC
MS-012, 0.150 inch Narrow
74LVX08MTCX
LVX08
TSSOP 14L
Tape and Reel
14-Lead Thin Shrink Small Outline Package,
JEDEC MO-153, 4.4 mm Wide
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
Description
An, Bn
On
Inputs
Outputs
© 1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.5.0
1
www.fairchildsemi.com
1 page  
Physical Dimensions
14
6.00
SOIC 14L
8.75
8.50
7.62
A
8
B
4.00
3.80
0.65
5.60
PIN ONE
INDICATOR
1
1.27
(0.33)
7
0.51
0.35
1.70
1.27
LAND PATTERN RECOMMENDATION
0.25 M C B A
1.75 MAX
1.50
1.25
R0.10
R0.10
8°
0°
SEE DETAIL A
0.25
0.10 C
0.10 C
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
0.50
0.25
A) THIS PACKAGE CONFORMS TO JEDEC
X 45°
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE FLASH OR BURRS.
D) LANDPATTERN STANDARD:
0.36
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.90
0.50
(1.04)
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 inch Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/M1/M14A.pdf.
© 1993 Fairchild Semiconductor Corporation
74LVX08 Rev. 1.5.0
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74LVX08.PDF ] | |
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