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PDF 74LVTH652WM Data sheet ( Hoja de datos )
| Número de pieza | 74LVTH652WM | |
| Descripción | Low Voltage Octal Transceiver/Register with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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April 2000
Revised April 2000
74LVTH652
Low Voltage Octal Transceiver/Register
with 3-STATE Outputs
General Description
The LVTH652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to HIGH
logic level. Output Enable pins (OEAB, OEBA) are pro-
vided to control the transceiver function. (See Functional
Description).
The LVTH652 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
This octal transceiver/register is designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVTH652 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintaining
low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 652
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH652WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVTH652MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation DS012018
www.fairchildsemi.com
1 page  
DC Electrical Characteristics
Symbol
Parameter
VIK Input Clamp Diode Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage
VOH Output HIGH Voltage
VOL Output LOW Voltage
II(HOLD)
II(OD)
II
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
VCC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
2.7
2.7
3.0
3.0
3.0
3.0
3.0
Control Pins
Data Pins
3.6
3.6
3.6
IOFF
IPU/PD
IOZL
IOZH
IOZH+
ICCH
ICCL
ICCZ
ICCZ+
Power OFF Leakage Current
Power Up/Down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
TA =−40°C to +85°C
Min Max
−1.2
2.0
0.8
VCC − 0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
75
−75
500
−500
10
±1
−5
1
±100
±100
−5
5
10
0.19
5
0.19
0.19
Units
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
∆ICC
Increase in Power Supply Current
(Note 6)
3.6
0.2 mA
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
II = −18 mA
VO ≤ 0.1V or
VO ≥ VCC − 0.1V
IOH = −100 µA
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
VI = 0.8V
VI = 2.0V
(Note 4)
(Note 5)
VI = 5.5V
VI = 0V or VCC
VI = 0V
VI = VCC
0V ≤ VI or VO ≤ 5.5V
VO = 0.5V to 3.0V
VI = GND or VCC
VO = 0.0V
VO = 3.6V
VCC < VO ≤ 5.5V
Outputs HIGH
A or B Port Outputs LOW
Outputs Disabled
VCC ≤ VO ≤ 5.5V
Outputs Disabled
One Input at VCC − 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 7)
Symbol
Parameter
VCC TA = 25°C
Units
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
3.3
−0.8
V
Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
Conditions
CL = 50 pF, RL = 500Ω
(Note 8)
(Note 8)
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