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PDF 74LVTH32373GX Data sheet ( Hoja de datos )
| Número de pieza | 74LVTH32373GX | |
| Descripción | Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary) | |
| Fabricantes | Fairchild Semiconductor | |
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Preliminary
August 2001
Revised August 2001
74LVT32373 • 74LVTH32373
Low Voltage 32-Bit Transparent Latch
with 3-STATE Outputs (Preliminary)
General Description
The LVT32373 and LVTH32373 contain thirty-two non-
inverting latches with 3-STATE outputs and are intended
for bus oriented applications. The device is byte controlled.
The flip-flops appear transparent to the data when the
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the setup time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the outputs are in a high impedance state.
The LVTH32373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT32373 and LVTH32373
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH32373),
also available without bushold feature (74LVT32373)
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Ordering Code:
Order Number Package Number
Package Description
74LVT32373GX
(Note 1)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LVTH32373GX
(Note 1)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
Note 1: BGA package available in Tape and Reel only.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500548
www.fairchildsemi.com
1 page  
DC Electrical Characteristics (Continued)
Preliminary
Symbol
Parameter
ICCH
ICCL
ICCZ
ICCZ+
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
(VCC1 or VCC2)
(VCC1 or VCC2)
(VCC1 or VCC2)
(VCC1 or VCC2)
VCC T A = −40°C to +85°C Units
(V) Min Max
3.6
0.19
mA
3.6 5 mA
3.6
0.19
mA
3.6
0.19
mA
∆ICC
Increase in Power Supply Current (VCC1 or VCC2)
(Note 7)
3.6
0.2 mA
Note 4: Applies to bushold versions only (74LVTH32373).
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
Outputs HIGH
Outputs LOW
Outputs Disabled
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
One Input at VCC − 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 8)
Symbol
Parameter
VCC TA = 25°C
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
VOLV
Quiet Output Minimum Dynamic VOL
3.3
−0.8
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
Units
V
V
Conditions
CL = 50 pF, RL = 500Ω
(Note 9)
(Note 9)
AC Electrical Characteristics
Symbol
Parameter
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPLZ
tPHZ
tS
tH
tW
Propagation Delay
Dn to On
Propagation Delay
LE to On
Output Enable Time
Output Disable Time
Setup Time, Dn to LE
Hold Time, Dn to LE
LE Pulse Width
TA = −40°C to +85°C, CL= 50pF, RL= 500Ω
VCC = 3.3V ± 0.3V
VCC = 2.7V
Min Max Min Max
1.5 3.9 1.5 4.3
1.5 3.8 1.5 4.2
1.9 4.2 1.9 4.4
1.6 4.3 1.6 4.8
1.3 4.3 1.3 4.9
1.0 4.3 1.0 5.1
1.5 4.7 1.5 4.8
2.0 5.0 2.0 5.4
1.0 0.8
1.0 1.1
3.0 3.0
Capacitance (Note 10)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = Open, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
ns
ns
ns
ns
ns
ns
ns
Units
pF
pF
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74LVTH32373GX.PDF ] | |
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