74LVTH162373 Datasheet PDF - Fairchild Semiconductor
Part Number | 74LVTH162373 | |
Description | Low Voltage 16-Bit Transparent Latch | |
Manufacturers | Fairchild Semiconductor | |
Logo | ||
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Revised June 2005
74LVTH162373
Low Voltage 16-Bit Transparent Latch with
3-STATE Outputs and
25: Series Resistors in the Outputs
General Description
The LVTH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LVTH162373 is designed with equivalent 25: series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
The LVTH162373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH162373 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs include equivalent series resistance of 25: to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s Functionally compatible with the 74 series 16373
s Latch-up performance exceeds 500 mA
s ESD performance:
Human-body model ! 2000V
Machine model ! 200V
Charged-device model ! 1000V
Ordering Code:
Order Number
Package
Number
Package Description
74LVTH162373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBES]
74LVTH162373MEX
(Note 1)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LVTH162373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74LVTH162373MTX
(Note 1)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation DS500354
www.fairchildsemi.com
|
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DC Electrical Characteristics (Continued)
Symbol
Parameter
ICCZ
Power Supply Current
VCC T A 40qC to 85qC Units
(V) Min Max
3.6
0.19
mA
'ICC
Increase in Power Supply Current
(Note 6)
3.6 0.2 mA
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
VCC d VO d 5.5V,
Outputs Disabled
One Input at VCC 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 7)
Symbol
Parameter
VCC TA 25qC
Units
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
VOLV
Quiet Output Minimum Dynamic VOL
3.3
0.8
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
V
V
Conditions
CL 50 pF, RL 500:
(Note 8)
(Note 8)
AC Electrical Characteristics
TA 40qC to 85qC, CL 50pF, RL 500:
Symbol
Parameter
VCC 3.3V r 0.3V
VCC 2.7V
Units
Min Max
Min Max
tPHL Propagation Delay
tPLH
Dn to On
1.3 4.8 1.3 5.3
1.4 4.8 1.4 5.1
ns
tPHL Propagation Delay
tPLH
LE to On
1.7 5.0 1.7 5.1
1.4 5.1 1.4 5.8
ns
tPZL
tPZH
Output Enable Time
1.6 5.0 1.6 6.0
1.0 5.4 1.0 6.6
ns
tPLZ
tPHZ
Output Disable Time
1.6 5.1 1.6 5.0
1.8 5.4 1.8 5.7
ns
tS Setup Time, Dn to LE
1.0 0.8 ns
tH Hold Time, Dn to LE
1.0 1.1 ns
tW LE Pulse Width
3.0 3.0 ns
tOSHL
tOSLH
Output to Output Skew (Note 9)
1.0 1.0
ns
1.0 1.0
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 10)
Symbol
Parameter
Conditions
CIN Input Capacitance
COUT
Output Capacitance
Note 10: Capacitance is measured at frequency f
VCC OPEN, VI 0V or VCC
VCC 3.0V, VO 0V or VCC
1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
5 www.fairchildsemi.com
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