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PDF 74LVT244MSA Data sheet ( Hoja de datos )
| Número de pieza | 74LVT244MSA | |
| Descripción | Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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July 1999
Revised August 1999
74LVT244 •74LVTH244
Low Voltage Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT244 and LVTH244 are octal buffers and line drivers
designed to be employed as memory address drivers,
clock drivers and bus oriented transmitters or receivers
which provide improved PC board density.
The LVTH244 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal buffers and line drivers are designed for low-
voltage (3.3V) VCC applications, but with the capability to
provide a TTL interface to a 5V environment. The LVT244
and LVTH244 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH244),
also available without bushold feature (74LVT244)
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 244
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVT244WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LVT244SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT244MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVT244MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH244WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LVTH244SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH244MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVTH244MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS500154
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
TA = −40°C to +85°C
CL = 50 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.7V
Units
Min Typ Max Min Max
(Note 10)
tPLH Propagation Delay Data to Output
tPHL
tPZH Output Enable Time
tPZL
tPHZ Output Disable Time
tPLZ
tOSHL
Output to Output Skew
tOSLH
(Note 11)
Note 10: All typical values are at VCC = 3.3V, TA = 25°C.
1.1
1.3
1.1
1.4
1.9
1.8
3.8 1.1 4.0
ns
3.9 1.3 4.2
4.5 1.1 5.3
ns
4.4 1.4 5.0
4.9 1.9 5.1
ns
4.4 1.8 4.4
1.0 1.0 ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance (Note 12)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
3
6
Units
pF
pF
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74LVT244MSA.PDF ] | |
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