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PDF 74LVT16244 Data sheet ( Hoja de datos )
| Número de pieza | 74LVT16244 | |
| Descripción | Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1999
Revised June 2005
74LVT16244 • 74LVTH16244
Low Voltage16-Bit Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT16244 and LVTH16244 contain sixteen non-invert-
ing buffers with 3-STATE outputs designed to be employed
as a memory and address driver, clock driver, or bus ori-
ented transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together
for 8-bit or 16-bit operation.
The LVTH16244 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT16244 and
LVTH16244 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16244),
also available without bushold feature (74LVT16244).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/64 mA
s Functionally compatible with the 74 series 16244
s Latch-up performance exceeds 500 mA
s ESD performance:
Human-body model !2000V
Machine model !200V
Charged-drive model !1000V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
Package
Number
Package Description
74LVT16244G
(Note 1)(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary)
74LVT16244MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16244MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16244G
(Note 1)(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH16244MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16244MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Ordering code “G” indicates Trays.
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation DS500151
www.fairchildsemi.com
1 page  
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74LVT16244.PDF ] | |
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