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PDF 74LVQ574T Data sheet ( Hoja de datos )
| Número de pieza | 74LVQ574T | |
| Descripción | OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74LVQ574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUTS NON INVERTING
s HIGH SPEED:
fMAX = 180 MHz (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.5 V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ574 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK) and an output enable input (OE).
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ574M
74LVQ574T
On the positive transition of the clock, the Q
outputs will be set to logic state that were setup
at the D inputs.
While the (OE) input is low, the 8 outputs will be
in al normal logic state (high or low logic level)
and while high level, the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flop, that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumpion.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/10
1 page  
74LVQ574
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symb ol
Parameter
T est Con ditio n
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
tPLH Propagation Delay Time
tPHL CK to Q
2.7
3.3(*)
7.5 17.0
6.0 11.0
18.0
12.0
ns
tPLZ Output Disable Time
tPHZ
2.7
3.3(*)
8.0 20.0
6.5 14.0
21.0
15.0
ns
tPZL Output Enable Time
tPZH
2.7
3.3(*)
8.0 18.0
6.5 12..0
19.0
13.0
ns
tw Clock pulse Width,
HIGH or LOW
2.7
3.3(*)
2.0 5.0
1.5 4.0
6.0 ns
4.0
tsL Setup Time D to CK
tsH HIGH or LOW
2.7
3.3(*)
0.0 2.5
0.0 2.0
3.0 ns
2.5
thL Hold Time D to CK
thH HIGH or LOW
2.7
3.3(*)
0.0 2.5
0.0 2.0
3.0 ns
2.5
fMAX Maximum Clock
Frequency
2.7
3.3(*)
80 150 70 MHz
100 180
90
tOSLH Output to Output Skew
tOSHL Time (note 1, 2)
2.7
3.3(*)
0.5 1.0
0.5 1.0
1.5 ns
1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
CIN Input Capacitance
3.3
4 pF
COUT Output Capacitance
3.3
10 pF
CPD Power Dissipation
3.3 fIN = 10 MHz
Capacitance (note 1)
15
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8(per FlipFlop)
5/10
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74LVQ574T.PDF ] | |
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