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PDF 74LVQ174 Data sheet ( Hoja de datos )
| Número de pieza | 74LVQ174 | |
| Descripción | HEX D-TYPE FLIP FLOP WITH CLEAR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74LVQ174
HEX D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
fMAX = 150 MHz (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.3 V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ174 is a low voltage CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and low noise
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ174M
74LVQ174T
3.3V applications.
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentely of the other inputs .
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
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1 page  
74LVQ174
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symb ol
Parameter
T est Con ditio n
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
tPLH Propagation Delay Time
tPHL CK to Q
2.7
3.3(*)
7.0 15.0
5.5 11.0
17.0
12.0
ns
tPHL Propagation Delay Time
CLR to Q
2.7
3.3(*)
8.5 16.0
7.0 12.0
18.0
13.0
ns
tw(L) CLR pulse Width, LOW
2.7
3.3(*)
1.0 7.0
1.0 5.5
10.0 ns
7.0
tw CK pulse Width, HIGH or
LOW, 2.7
3.3(*)
1.0 7.0
10.0 ns
1.0 5.5
7.0
tsL Setup Time D to CK HIGH
2.7
tsH or LOW
3.3(*)
-0.5 8.0
-0.4 6.5
10.0 ns
7.0
thL Hold Time D to CK HIGH
thH or LOW
2.7
3.3(*)
0.5 4.0
0.4 3.0
4.5 ns
3.0
tREM Recovery Time CLR to CK
2.7
3.3(*)
0.5 3.5
0.4 2.5
3.5 ns
2.5
fMAX Maximum Clock Frequency 2.7
3.3(*)
60 150 50 MHz
90 150
70
tOSLH Output to Output Skew
tOSHL Time (note 1, 2)
2.7
3.3(*)
0.5 1.0
0.5 1.0
1.5 ns
1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
CIN Input Capacitance
3.3
5 pF
CPD Power Dissipation
Capacitance (note 1)
3.3 fIN = 10 MHz
23
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/6(per flipflop)
5/10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74LVQ174.PDF ] | |
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