74LVC574A Datasheet PDF - NXP Semiconductors
| Part Number | 74LVC574A | |
| Description | Octal D-type flip-flop | |
| Manufacturers | NXP Semiconductors | |
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74LVC574A
Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive
edge-trigger; 3-state
Rev. 5 — 18 December 2012
Product data sheet
1. General description
The 74LVC574A is an octal D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock (CP) and an Output
Enable (OE) input are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW to HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops are available at the outputs. When
OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input
does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V or 5 V applications.
The 74LVC574A is functionally identical to the 74LVC374A, but has a different pin
arrangement.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when VCC = 0 V
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Flow-through pin-out architecture
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
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NXP Semiconductors
74LVC574A
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
6. Functional description
Table 3. Functional table[1]
Operating modes
Input
OE
Load and read register
L
L
Load register and disable outputs H
H
CP
Dn
l
h
l
h
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
= LOW to HIGH clock transition
Z = high-impedance OFF-state
7. Limiting values
Internal
flip-flop
L
H
L
H
Output
Qn
L
H
Z
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max
Unit
VCC
IIK
VI
IOK
VO
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0
VO > VCC or VO < 0
output HIGH or LOW state
VO = 0 V to VCC
Tamb = 40 C to +125 C
0.5
50
[1] 0.5
-
[2] 0.5
-
-
100
65
[3] -
+6.5
-
+6.5
50
VCC + 0.5
50
100
-
+150
500
V
mA
V
mA
V
mA
mA
mA
C
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
74LVC574A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 December 2012
© NXP B.V. 2012. All rights reserved.
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| Information | Total 19 Pages | |
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