74LVC1G58 Datasheet PDF - NXP Semiconductors
Part Number | 74LVC1G58 | |
Description | Low-power configurable multiple function gate | |
Manufacturers | NXP Semiconductors | |
Logo | ||
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Low-power configurable multiple function gate
Rev. 01 — 15 September 2004
Product data sheet
1. General description
The 74LVC1G58 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC1G58 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND.
The three inputs (A, B and C) are capable of transforming slowly changing input signals
into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The
difference between the positive voltage VT+ and the negative voltage VT− is defined as the
hysteresis voltage VH.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant input/output for interfacing with 5 V logic
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8B/JESD36 (2.7 V to 3.6 V).
s ±24 mA output drive (VCC = 3.0 V)
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C.
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Philips Semiconductors
74LVC1G58
Low-power configurable multiple function gate
VCC
A
C
Y
1 6C
25
A
C
Y
A3
4Y
001aab690
Fig 6. 2-input AND gate with inverted C
input or 2-input NOR gate with
inverted A input.
VCC
A
C
Y
1 6C
25
A
C
Y
A3
4Y
001aab691
Fig 7. 2-input OR gate or 2-input NAND
gate with both inputs inverted.
VCC
B 1 6C
B
C
Y
25
3 4Y
001aab692
Fig 8. 2-input XOR gate.
AY
Fig 9. Buffer.
VCC
1
2
A3
6
5
4Y
001aab693
VCC
Fig 10. Inverter.
B1
6
BY
25
3 4Y
001aab694
9. Limiting values
9397 750 13852
Product data sheet
Table 7: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max
Unit
VCC supply voltage
−0.5 +6.5
V
IIK input diode current VI < 0 V
- −50
mA
VI input voltage
[1] −0.5 +6.5
V
IOK
output diode current
VO > VCC or VO < 0 V
- ±50
mA
VO output voltage
active mode
[1] [2] −0.5 +6.5
V
Power-down mode
[1] [2] −0.5 +6.5
V
IO
output source or sink
VO = 0 V to VCC
current
- ±50
mA
Rev. 01 — 15 September 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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