PDF MC14013B Data sheet ( Hoja de datos )

Número de pieza	MC14013B
Descripción	Dual Type D Flip-Flop
Fabricantes	ON Semiconductor
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No Preview Available ! MC14013B Dual Type D Flip-Flop The MC14013B dual type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each flip−flop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip−flops for counter and toggle applications. Features • Static Operation • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Logic Edge−Clocked Flip−Flop Design • Logic State is Retained Indefinitely with Clock Level either High or Low; Information is Transferred to the Output only on the Positive−going Edge of the Clock Pulse • Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range • Pin−for−Pin Replacement for CD4013B • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free and are RoHS Compliant http://onsemi.com SOIC−14 D SUFFIX CASE 751A SOEIAJ−14 F SUFFIX CASE 965 TSSOP−14 DT SUFFIX CASE 948G PIN ASSIGNMENT QA 1 QA 2 CA 3 RA 4 DA 5 SA 6 VSS 7 14 VDD 13 QB 12 QB 11 CB 10 RB 9 DB 8 SB MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD Vin, Vout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) −0.5 to +18.0 −0.5 to VDD + 0.5 V V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MARKING DIAGRAMS 14 14013BG AWLYWW 1 SOIC−14 14 MC14013B ALYWG 1 SOEIAJ−14 14 14 013B ALYW G G 1 TSSOP−14 A WL, L YY, Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 10 1 Publication Order Number: MC14013B/D 1 page MC14013B 20 ns D tsu (H) C 90% 50% 10% tsu (L) th tWH tPLH Q 1 fcl 90% 50% 10% tTLH Inputs R and S low. 20 ns 90% 50% 10% tWL VDD VSS 20 ns VDD VSS tPHL tTHL VOH VOL Figure 1. Dynamic Signal Waveforms (Data, Clock, and Output) 20 ns SET OR RESET 90% tw CLOCK tPLH tPHL Q OR Q 20 ns 50% 10% 20 ns 90% trem 50% tw 50% VDD VSS 20 ns VDD 10% VSS VOH VOL Figure 2. Dynamic Signal Waveforms (Set, Reset, Clock, and Output) D CLOCK CLOCK TYPICAL APPLICATIONS n−STAGE SHIFT REGISTER 12 DQ DQ CQ CQ nth DQ CQ Q BINARY RIPPLE UP−COUNTER (Divide−by−2n) 12 nth DQ DQ DQ CQ CQ CQ Q T FLIP-FLOP CLOCK MODIFIED RING COUNTER (Divide−by−(n+1)) 12 nth DQ DQ DQ CQ CQ CQ Q http://onsemi.com 5 5 Page

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