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Número de pieza | PEF20324 | |
Descripción | ICs for Communications | |
Fabricantes | Infineon Technologies AG | |
Logotipo | ||
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ICs for Communications
Multichannel Network Interface Controller for HDLC + Extensions
MUNICH128X
PEB 20324 Version 2.2
Hardware Reference Manual 04.99
DS 1
1 page PEB 20324
PEF 20324
List of Figures
Page
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 2-1
Figure 3-1
Figure 3-1
Figure 3-2
Figure 5-1
Figure 5-2
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 5-10
Figure 5-11
Figure 6-1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
System Integration of the MUNICH128X in PCI-Based System . . . . . .12
System Integration of the MUNICH128X in De-multiplexed System . . .13
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
System Integration of the MUNICH128X in PCI-Based System . . . . . .34
System Integration of the MUNICH128X in De-multiplexed System . . .35
Power-up and Power-down scenarios . . . . . . . . . . . . . . . . . . . . . . . . . .37
Power-Failure scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . . .43
PCI Output Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . .44
PCI Input Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . . .44
PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
PCI Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Master Single READ Transaction followed by a Master Single
WRITE Transaction in De-multiplexed Bus Configuration . . . . . . . . . . .51
Master Burst WRITE/READ Access in De-multiplexed Bus
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . . .57
Hardware Reference Manual
5
04.99
5 Page 1.2 Logic Symbol
•
JTAG Test
Interface
PCI
BUS
AD(31:0)
C/BE(3:0)
PAR
FRAME
IRDY
TRDY
STOP
IDSEL
DEVSEL
PERR
SERR
REQ
GNT
CLK
RST
INTA
MUNICH128X
PEB 20324
PEF 20324
A(27:2)
DPCI(1:0) W/R
(de-multiplexed address bus)
Control and Address Bus Extension
for De-multiplexed Bus Interface
Figure 1-2 Logic Symbol
PEB 20324
PEF 20324
Introduction
TxD0
RxD0
TSP0
RSP0
TXDEN0
TxCLK0
RxCLK0
Serial
Channel 0
(PCM0)
Serial
Channel 1
(PCM1)
Serial
Channel 2
(PCM2)
Serial
Channel 3
(PCM3)
Hardware Reference Manual
11
04.99
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet PEF20324.PDF ] |
Número de pieza | Descripción | Fabricantes |
PEF20321 | Multichannel Network Interface Controller for HDLC | Infineon Technologies AG |
PEF20324 | ICs for Communications | Infineon Technologies AG |
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