PDF TDA10085HT Data sheet ( Hoja de datos )

Número de pieza	TDA10085HT
Descripción	Single chip DVB-S/DSS channel receiver
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET TDA10085HT Single chip DVB-S/DSS channel receiver Product speciﬁcation Supersedes data of 2000 March 16 File under Integrated Circuits, IC02 2001 Aug 31 1 page Philips Semiconductors Single chip DVB-S/DSS channel receiver Product speciﬁcation TDA10085HT 6 PINNING SYMBOL XIN XOUT VDDI PLLVCC PLLGND DGND DVCC VDDI VSSI VDD3 AVS VIN2 VREFN VREFP VIN1 AVD SADDR0 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TMD ENSERI IICDIV CTRL1 CTRL2 VSSE VDDE5 VSSI 2001 Aug 31 18 19 20 21 22 23 24 25 TYPE I I supply supply ground ground supply supply ground supply ground I O O I supply I I I I OD OD ground supply ground DESCRIPTION crystal oscillator input and output pins; in a typical application, a fundamental oscillator crystal is connected between pins XIN and XOUT; see note 1 digital core supply voltage (typically 1.8 V) analog supply voltage for the PLL (typically 3.3 V) analog ground for the PLL digital PLL core ground voltage; see note 2 digital PLL core supply voltage (typically 1.8 V) digital ADC supply voltage (typically 1.8 V) digital ADC ground voltage; see note 2 analog ADC supply voltage (typically 3.3 V) analog ground voltage analog signal input for channel Q; see note 1 negative analog voltage reference output (typically 1.25 V); a decoupling capacitor (typically 0.1 µF) must be placed as close as possible between VREFN and GND positive analog voltage reference output (typically 2 V); a decoupling capacitor (typically 0.1 µF) must be placed as closed as possible between VREFP and GND analog signal input for channel I; see note 1 analog supply voltage (typically 3.3 V); a 0.1 µF decoupling capacitor must be placed between AVD and AVS SADDR0 input signal is the LSB of the I2C-bus address of the TDA10085; other bits of the address are set internally to 000111, therefore the complete I2C-bus address is (MSB to LSB): 0, 0, 0, 1, 1, 1 plus the SADDR0 bit; see note 1 test input; must be connected to ground for normal operation; see note 1 enable serial interface input; when HIGH, the serial transport stream is present on the boundary scan pins (TRST, TDO, TCK, TDI and TMS); when LOW, the boundary scan pins are available; note 1 input to select the I2C-bus internal system clock frequency (depends on the crystal frequency); internal I2C-bus clock is XIN when IICDIV = 0 and XIN/4 if IICDIV = 1; see note 1 control line output 1; this pin function is directly programmable through the I2C-bus interface; default value is logic 1; open-drain output requiring an external pull-up resistor to 3.3 V or to 5 V control line output 2; this pin function is directly programmable through the I2C-bus interface; default value is logic 1; open-drain output requiring an external pull-up resistor to 3.3 V or to 5 V digital ground voltage; see note 2 digital 5 V supply voltage; required for the 5 V tolerance of inputs digital core ground voltage; see note 2 5 5 Page Philips Semiconductors Single chip DVB-S/DSS channel receiver 10 APPLICATION INFORMATION Product speciﬁcation TDA10085HT handbook, full pagewidth from LNB MIXER × LO 90° PHASE SHIFT PLL × MIXER VAGC XIN 30 VIN1 15 1 XOUT 2 51-54 8 59-62 DO[7-0] VREFP 14 VREFN 13 TDA10085HT 50 49 OCLK DEN GND VIN2 12 48 47 28 29 32 33 SDA-0 SCL-0 SDA SCL UNCOR PSYNC MGU428 The TDA10085 can receive a 4 MHz clock signal delivered by the PLL synthesizer, or can generate the sampling clock from a crystal connected between XIN and XOUT. Bypass capacitors (0.1 µF) should be placed close to ADC voltage references VREFP and VREFN. Fig.3 Front-end receiver schematic. handbook, full pagewidth LNB SUPPLY GENERATION VAGC CTRL1 22K 30 21 63 VIN1 LNB channel I TUNER channel Q 15 VIN2 12 TDA10085 51-54 MPEG2 59-62 8 transport stream DO[7-0] 28 29 32 33 SDA-0 SCL-0 SDA SCL MGU429 2001 Aug 31 Fig.4 Typical use of CTRL1 and 22K outputs. 11 11 Page

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