74LS221 Datasheet PDF - Fairchild Semiconductor
Part Number | 74LS221 | |
Description | Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs | |
Manufacturers | Fairchild Semiconductor | |
Logo | ||
There is a preview and 74LS221 download ( pdf file ) link at the bottom of this page. Total 8 Pages |
Preview 1 page No Preview Available ! August 1986
Revised April 2000
DM74LS221 Dual Non-Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
The DM74LS221 is a dual monostable multivibrator with
Schmitt-trigger input. Each device has three inputs permit-
ting the choice of either leading-edge or trailing-edge trig-
gering. Pin (A) is an active-LOW trigger transition input and
pin (B) is an active-HIGH transition Schmitt-trigger input
that allows jitter free triggering for inputs with transition
rates as slow as 1 volt/second. This provides the input with
excellent noise immunity. Additionally an internal latching
circuit at the input stage also provides a high immunity to
VCC noise. The clear (CLR) input can terminate the output
pulse at a predetermined time independent of the timing
components. This (CLR) input also serves as a trigger
input when it is pulsed with a low level pulse transition
( ). To obtain the best and trouble free operation from
this device please read operating rules as well as the Fair-
child Semiconductor one-shot application notes carefully
and observe recommendations.
Features
s A dual, highly stable one-shot
s Compensated for VCC and temperature variations
s Pin-out identical to DM74LS123 (Note 1)
s Output pulse width range from 30 ns to 70 seconds
s Hysteresis provided at (B) input for added noise
immunity
s Direct reset terminates output pulse
s Triggerable from CLEAR input
s DTL, TTL compatible
s Input clamp diodes
Note 1: The pin-out is identical to DM74LS123 but, functionally it is not;
refer to Operating Rules #10 in this datasheet.
Ordering Code:
Order Number Package Number
Package Description
DM74LS221M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS221SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS221N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
CLEAR
A
B
Q
Q
L XXLH
X HXLH
X
H
H
↑ (Note 2)
X
L
↓
L
L
↑
H
H
L
H
H = HIGH Logic Level
L = LOW Logic Level
X = Can Be Either LOW or HIGH
↑ = Positive Going Transition
↓ = Negative Going Transition
= A Positive Pulse
= A Negative Pulse
Note 2: This mode of triggering requires first the B input be set from a
LOW-to-HIGH level while the CLEAR input is maintained at logic LOW
level. Then with the B input at logic HIGH level, the CLEAR input whose
positive transition from LOW-to-HIGH will trigger an output pulse.
© 2000 Fairchild Semiconductor Corporation DS006409
www.fairchildsemi.com
|
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Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI Input Clamp Voltage
VCC = Min, II = −18 mA
VOH HIGH Level
VCC = Min, IOH = Max
Output Voltage
VIL = Max, VIH = Min
VOL LOW Level
VCC = Min, IOL = Max
Output Voltage
VIL = Max, VIH = Min
VCC = Min, IOL = 4 mA
II
Input Current @ Max Input Voltage
VCC = Max, VI = 7V
IIH HIGH Level Input Current
VCC = Max, VI = 2.7V
IIL LOW Level
VCC = Max
A1, A2
Input Current
VI = 0.4V
B
Clear
2.7
IOS Short Circuit
Output Current
VCC = Max
(Note 6)
−20
ICC Supply Current
VCC = Max
Quiescent
Triggered
Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
tPLH
tPLH
tPHL
tPHL
tPLH
tPHL
tW(out)
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Output Pulse
Width Using Zero
Timing Capacitance
tW(out)
Output Pulse
Width Using External
Timing Resistor
From (Input)
To (Output)
A1, A2
to Q
B
to Q
A1, A2
to Q
B
to Q
Clear to
Q
Clear
to Q
A1, A2
to Q, Q
A1, A2
to Q, Q
Conditions
CEXT = 80 pF
REXT = 2 kΩ
CL = 15 pF
RL = 2 kΩ
CEXT = 0
REXT = 2 kΩ
RL = 2 kΩ
CL = 15 pF
CEXT = 100 pF
REXT = 10 kΩ
RL = 2 kΩ
CL = 15 pF
CEXT = 1 µF
REXT = 10 kΩ
RL = 2 kΩ
CL = 15 pF
CEXT = 80 pF
REXT = 2 kΩ
RL = 2 kΩ
CL = 15 pF
Typ
(Note 5)
3.4
0.35
4.7
19
Max
−1.5
0.5
0.4
0.1
20
−0.4
−0.8
−0.8
−100
11
27
Min Max
70
55
80
65
65
55
20 70
600 750
6 7.5
70 150
Units
V
V
V
mA
µA
mA
mA
mA
Units
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
5 www.fairchildsemi.com
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