PDF 74LS181 Data sheet ( Hoja de datos )

Número de pieza	74LS181
Descripción	4-Bit Arithmetic Logic Unit
Fabricantes	Fairchild Semiconductor
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No Preview Available ! October 1988 Revised April 2000 DM74LS181 4-Bit Arithmetic Logic Unit General Description The DM74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations. Features s Provides 16 arithmetic operations: add, subtract, com- pare, double, plus twelve other arithmetic operations s Provides all 16 logic operations of two variables: exclusive-OR, compare, AND, NAND, OR, NOR, plus ten other logic operations s Full lookahead for high speed arithmetic operation on long words Ordering Code: Order Number Package Number Package Description DM74LS181N N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Logic Symbols Connection Diagram Active High Operands Active Low Operands VCC = Pin 24 GND = Pin 12 Pin Descriptions Pin Names Description A0–A3 B0–B3 S0–S3 M Cn F0–F3 A=B G P Cn+4 Operand Inputs (Active LOW) Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output © 2000 Fairchild Semiconductor Corporation DS009821 www.fairchildsemi.com 1 page Switching Characteristics VCC = 5V, TA = 25°C Symbol Parameter Conditions tPLH Propagation Delay tPHL Cn to Cn+4 tPLH Propagation Delay tPHL Cn to F tPLH Propagation Delay tPHL A or B to G (Sum) tPLH Propagation Delay tPHL A or B to G (Diff) tPLH Propagation Delay tPHL A or B to P (Sum) tPLH Propagation Delay tPHL A or B to P (Diff) tPLH Propagation Delay tPHL Ai or Bi to Fi(Sum) tPLH Propagation Delay tPHL Ai or Bi to Fi(Diff) tPLH Propagation Delay tPHL A or B to F (Logic) tPLH Propagation Delay tPHL A or B to Cn+4 (Sum) tPLH Propagation Delay tPHL A or B to Cn+4 (Diff) tPLH Propagation Delay tPHL A or B to A = B M = GND M = GND M, S1, S2 = GND; S1, S3 = 4.5V M, S0, S3 = GND; S1, S2 = 4.5V M, S1, S2 = GND; S0, S3 = 4.5V M, S0, S3 = GND; S1, S2 = 4.5V M, S1, S2 = GND; S0, S3 = 4.5V M, S0, S3 = GND; S1, S2 = 4.5V M = 4.5V M, S1, S2 = GND; S0, S3 = 4.5V M, S0, S3 = GND; S1, S2 = 4.5V M, S0, S3 = GND; S1, S2 = 4.5V; RL = 2 kΩ to 5.0V CL = 15 pF Min Max 27 20 26 20 29 23 32 26 30 30 30 33 32 25 32 33 33 29 38 38 41 41 50 62 Sum Mode Test Table 1 Function Inputs S0 = S3 = 4.5V, S1 = S2 = M = 0V Input Symbol Under Test Other Input Same Bit Apply Apply 4.5V GND tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Ai Bi None Bi Ai None A B None B A None A None B B None A A None B B None A Cn None None Other Data Inputs Apply 4.5V Remaining A and B Remaining A and B None None Remaining B Remaining B Remaining B Remaining B All A Apply GND Cn Cn Remaining A and B, Cn Remaining A and B, Cn Remaining A, Cn Remaining A, Cn Remaining A, Cn Remaining A, Cn All B Units ns ns ns ns ns ns ns ns ns ns ns ns Output Under Test Fi Fi P P G G Cn+4 Cn+4 Any F or Cn+4 5 www.fairchildsemi.com 5 Page

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