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PDF 74LS164 Data sheet ( Hoja de datos )
| Número de pieza | 74LS164 | |
| Descripción | 8-Bit Serial-Input/Parallel-Output Shift Register | |
| Fabricantes | System Logic Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74LS164 (archivo pdf) en la parte inferior de esta página. Total 4 Páginas | ||
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SL74LS164
8-Bit Serial-Input/Parallel-Output
Shift Register
This 8-bit shift register features gated serial inputs and an
asynchronous reset. The gated serial inputs (A and B) permit complete
control over incoming data as a low at either (or both) input(s) inhibits
entry of the new data and resets the first flip flop to the low level at the
next clock pulse. A high level input enables the other input which will
then determine the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is high or low, but only information
meeting the setup requirements will be entered clocking occurs or the
low-to-high level transition of the clock input. All inputs are diode-
clamped to minimize transmission-line effects.
• Gated (Enable/Disable) Serial Inputs
• Fully Buffered Clock and Serial Inputs
• Asynchronous Clear
ORDERING INFORMATION
SL74LS164N Plastic
SL74LS164D SOIC
TA =0° to 70°C
for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
SLS
System Logic
Semiconductor
FUNCTION TABLE
Inputs
Outputs
Reset Clock A1 A2 QA QB ... QH
L
X
XX
L L ... L
H
XX
no change
H
HD
D QAn ... QGn
H
DH
D QAn ... QGn
H
LL
L QAn ... QGn
D = data input
X = don’t care
QAn - QGn = data shifted from the previous stage on a
rising edge at the clock input.
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet 74LS164.PDF ] | |
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