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PDF 74LS164 Data sheet ( Hoja de datos )

Número de pieza 74LS164
Descripción LOW POWER SCHOTTKY
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



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No Preview Available ! 74LS164 Hoja de datos, Descripción, Manual

SN74LS164
Serial-In Parallel-Out
Shift Register
The SN74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift
Register. Serial data is entered through a 2-Input AND gate
synchronous with the LOW to HIGH transition of the clock. The
device features an asynchronous Master Reset which clears the
register setting all outputs LOW independent of the clock. It utilizes
the Schottky diode clamped process to achieve high speeds and is fully
compatible with all ON Semiconductor TTL products.
Typical Shift Frequency of 35 MHz
Asynchronous Master Reset
Gated Serial Data Input
Fully Synchronous Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
ESD > 3500 Volts
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 0.4
8.0
mA
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
14
1
PLASTIC
N SUFFIX
CASE 646
14
1
SOIC
D SUFFIX
CASE 751A
ORDERING INFORMATION
Device
Package
Shipping
SN74LS164N 14 Pin DIP 2000 Units/Box
SN74LS164D
14 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS164/D

1 page




74LS164 pdf
SN74LS164
AC WAVEFORMS
*The shaded areas indicate when the input is permitted to change for predictable output performance.
I/fmax
tW
1.3 V 1.3 V 1.3 V
CP
tPHL tPLH
Q
1.3 V
1.3 V
CONDITIONS: MR = H
MR
1.3 V
1.3 V
tW trec
1.3 V
CP
tPHL
Q
1.3 V
Figure 1. Clock to Output Delays
and Clock Pulse Width
Figure 2. Master Reset Pulse Width,
Master Reset to Output Delay and
Master Reset to Clock Recovery Time
1/fmax
tW
CP 1.3 V 1.3 V 1.3 V 1.3 V
ts(H) th(H) ts(L) th(L)
D * 1.3 V 1.3 V
1.3 V 1.3 V
Q 1.3 V 1.3 V
Figure 3. Data Setup and Hold Times
http://onsemi.com
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