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PDF 74LCX374 Data sheet ( Hoja de datos )

Número de pieza 74LCX374
Descripción LOW-VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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No Preview Available ! 74LCX374 Hoja de datos, Descripción, Manual

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage CMOS
Octal D-Type Flip-Flop
With 5V-Tolerant Inputs and Outputs
(3-State, Non-Inverting)
The MC74LCX374 is a high performance, non–inverting octal D–type
flip–flop operating from a 2.7 to 3.6V supply. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5V allows MC74LCX374 inputs to be
safely driven from 5V devices.
The MC74LCX374 consists of 8 edge–triggered flip–flops with
individual D–type inputs and 3–state true outputs. The buffered clock and
buffered Output Enable (OE) are common to all flip–flops. The eight
flip–flops will store the state of individual D inputs that meet the setup and
hold time requirements on the LOW–to–HIGH Clock (CP) transition. With
the OE LOW, the contents of the eight flip–flops are available at the
outputs. When the OE is HIGH, the outputs go to the high impedance
state. The OE input level does not affect the operation of the flip–flops.
Designed for 2.7 to 3.6V VCC Operation
5V Tolerant — Interface Capability With 5V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0V
LVTTL Compatible
LVCMOS Compatible
24mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10µA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500mA
ESD Performance: Human Body Model >2000V; Machine Model >200V
Pinout: 20–Lead (Top View)
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
MC74LCX374
LOW–VOLTAGE CMOS
OCTAL D–TYPE FLIP–FLOP
20
1
20
1
20
1
20
1
DW SUFFIX
PLASTIC SOIC
CASE 751D–04
M SUFFIX
PLASTIC SOIC EIAJ
CASE 967–01
SD SUFFIX
PLASTIC SSOP
CASE 940C–03
DT SUFFIX
PLASTIC TSSOP
CASE 948E–02
PIN NAMES
Pins
Function
OE
CP
D0–D7
O0–O7
Output Enable Input
Clock Pulse Input
Data Inputs
3–State Outputs
11/96
© Motorola, Inc. 1996
1
REV 3

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74LCX374 pdf
MC74LCX374
Dn
ts
CP
On
th
1.5V
fmax
tPLH, tPHL
1.5V
2.7V
1.5V
0V
2.7V
0V
VOH
VOL
WAVEFORM 1 – PROPAGATION DELAYS, SETUP AND HOLD TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
OE
tPZH
On
1.5V
tPHZ
1.5V
1.5V
tPZL
On
tPLZ
1.5V
2.7V
0V
VCC
VOH – 0.3V
0V
3.0V
VOL + 0.3V
GND
WAVEFORM 2 – OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
CP 1.5V
tw
2.7V
1.5V
0V
CP
PULSE
GENERATOR
tw
1.5V
1.5V
WAVEFORM 3 – PULSE WIDTH
tR = tF = 2.5ns (or fast as required) from 10% to 90%;
Output requirements: VOL 0.8V, VOH 2.0V
2.7V
0V
Figure 1. AC Waveforms
VCC
DUT
RT
R1
CL RL
6V
OPEN
GND
LCX DATA
BR1339 — REV 3
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V
Open Collector/Drain tPLH and tPHL
6V
tPZH, tPHZ
GND
CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500or equivalent
RT = ZOUT of pulse generator (typically 50)
Figure 2. Test Circuit
5
MOTOROLA

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