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74LCX245MTR Datasheet PDF - ST Microelectronics

Part Number 74LCX245MTR
Description LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
Manufacturers ST Microelectronics 
Logo ST Microelectronics Logo 

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74LCX245MTR datasheet, circuit
74LCX245
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER
(3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
s 5V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED:
tPD = 7.0 ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX245 is a low voltage CMOS OCTAL
BUS TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LCX245MTR
74LCX245TTR
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
This IC is intended for two way asynchronous
communication between data buses; the direction
of data transmission is determined by DIR input.
The enable input G can be used to disable the
device so that the buses are effectively isolated.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Z state must
be held HIGH or LOW.
Figure 1: Pin Connection And IEC Logic Symbols
September 2004
Rev. 4
1/13

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74LCX245MTR equivalent
74LCX245
Table 8: AC Electrical Characteristics
Test Condition
Value
Symbol
Parameter
tPLH tPHL
tPZL tPZH
Propagation Delay
Time
Output Enable Time
tPLZ tPHZ Output Disable Time
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
VCC
(V)
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
3.0 to 3.6
CL RL ts = tr
(pF) () (ns)
50 500 2.5
50 500 2.5
50 500 2.5
50 500 2.5
-40 to 85 °C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
Max.
8.0
7.0
9.5
8.5
8.5
7.5
1.0
-55 to 125 °C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
Max.
9.2
8.1
10.7
9.7
9.7
8.7
1.0
Unit
ns
ns
ns
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics
Test Condition
Value
Symbol
Parameter
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(note 1)
VCC
(V)
3.3
3.3
3.3
VIN = 0 to VCC
VIN = 0 to VCC
fIN = 10MHz
VIN = 0 or VCC
TA = 25 °C
Min. Typ. Max.
6
12
45
Unit
pF
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
5/13

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