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74LCX162373 Datasheet PDF - Fairchild Semiconductor

Part Number 74LCX162373
Description Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs and 26 Series Resistor
Manufacturers Fairchild Semiconductor 
Logo Fairchild Semiconductor Logo 

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74LCX162373 datasheet, circuit
February 2001
Revised August 2001
74LCX162373
Low Voltage 16-Bit Transparent Latch
with 5V Tolerant Inputs and Outputs
and 26Series Resistor
General Description
The LCX162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCX162373 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment. The 26series resistor in the output helps
reduce output overshoot and undershoot.
The LCX162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
I 5V tolerant inputs and outputs
I 2.3V–3.6V VCC specifications provided
I Equivalent 26series resistor outputs
I 6.2 ns tPD max (VCC = 3.3V), 20 µA ICC max
I Power down high impedance inputs and outputs
I Supports live insertion/withdrawal (Note 1)
I ±12 mA output drive (VCC = 3.0V)
I Implements patented noise/EMI reduction circuitry
I Latch-up performance exceeds 500 mA
I ESD performance:
Human body model > 2000V
Machine model > 200V
I Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX162373GX
(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LCX162373MEA
(Note 3)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCX162373MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500443
www.fairchildsemi.com

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74LCX162373 equivalent
DC Electrical Characteristics (Continued)
Symbol
Parameter
IOFF Power-Off Leakage Current
ICC Quiescent Supply Current
ICC
Increase in ICC per Input
Note 7: Outputs disabled or 3-STATE only.
Conditions
VI or VO = 5.5V
VI = VCC or GND
3.6V VI, VO 5.5V (Note 7)
VIH = VCC 0.6V
VCC
(V)
0
2.3 3.6
2.3 3.6
2.3 3.6
TA = −40°C to +85°C
Min Max
10
20
±20
500
Units
µA
µA
µA
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500
Symbol
Parameter
VCC = 3.3V ± 0.3V
CL = 50 pF
VCC = 2.7V
CL = 50 pF
VCC = 2.5V ± 0.2V
CL = 30 pF
Units
Min Max Min Max Min Max
tPHL Propagation Delay
tPLH
In to On
1.5 6.2 1.5 6.7 1.5 7.4
ns
1.5 6.2 1.5 6.7 1.5 7.4
tPHL Propagation Delay
tPLH
LE to On
1.5 6.3 1.5 7.2 1.5 7.6
ns
1.5 6.3 1.5 7.2 1.5 7.6
tPZL
tPZH
Output Enable Time
1.5 6.9 1.5 7.3 1.5 9.0
ns
1.5 6.9 1.5 7.3 1.5 9.0
tPLZ
tPHZ
Output Disable Time
1.5 6.0 1.5 6.3 1.5 7.2
ns
1.5 6.0 1.5 6.3 1.5 7.2
tS Setup Time, In to LE
2.5 2.5 3.0 ns
tH Hold Time, In to LE
1.5 1.5 2.0 ns
tW LE Pulse Width
3.0 3.0 3.5 ns
tOSHL
tOSLH
Output to Output Skew (Note 8)
1.0
1.0
ns
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
Capacitance
Conditions
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
VCC
TA = 25°C
Units
(V) Typical
3.3 0.35
V
2.5 0.25
3.3 0.35
2.5 0.25
V
Symbol
CIN
COUT
CPD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = Open, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
Typical
7
8
20
Units
pF
pF
pF
5 www.fairchildsemi.com

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