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74LCX139 Datasheet PDF - ST Microelectronics

Part Number 74LCX139
Description LOW VOLTAGE CMOS DUAL 2 TO 4 DECODER/DEMULTIPLEXER
Manufacturers ST Microelectronics 
Logo ST Microelectronics Logo 

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74LCX139 datasheet, circuit
74LCX139
LOW VOLTAGE CMOS
DUAL 2 TO 4 DECODER/DEMULTIPLEXER
s 5V TOLERANT INPUTS
s HIGH SPEED:
tPD = 6.2ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 139
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX139 is a low voltage CMOS DUAL 2
TO 4 LINE DECODER/DEMULTIPLEXER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology.
It is ideal for low power and high speed 3.3V
applications; it can be interfaced to 5V signal
environment for inputs.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LCX139MTR
74LCX139TTR
The active low enable input can be used for gating
or as a data input for demultiplexing applications.
While the enable input is held high, all four outputs
are high independently of the other inputs.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
September 2004
Rev. 3
1/12

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74LCX139 equivalent
74LCX139
Table 8: Capacitive Characteristics
Test Condition
Value
Symbol
Parameter
CIN Input Capacitance
CPD Power Dissipation Capacitance
(note 1)
VCC
(V)
3.3
3.3
VIN = 0 to VCC
fIN = 10MHz
VIN = 0 or VCC
TA = 25 °C
Min. Typ. Max.
6
26
Unit
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per gate)
Figure 5: Test Circuit
CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = 500or equivalent
RT = ZOUT of pulse generator (typically 50)
Figure 6: Waveform - Propagation Delays For Inverting Outputs (f=1MHz; 50% duty cycle)
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Information Total 12 Pages
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