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What is 74LCX112?

This electronic component, produced by the manufacturer "Fairchild Semiconductor", performs the same function as "Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs".


74LCX112 Datasheet PDF - Fairchild Semiconductor

Part Number 74LCX112
Description Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Manufacturers Fairchild Semiconductor 
Logo Fairchild Semiconductor Logo 


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No Preview Available ! 74LCX112 datasheet, circuit

June 1998
Revised March 1999
74LCX112
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop
with 5V Tolerant Inputs
General Description
The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-
pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,
Q outputs. These devices are edge sensitive and change
state on the negative going transition of the clock pulse.
Clear and preset are independent of the clock and accom-
plished by a low logic level on the corresponding input.
LCX devices are designed for low voltage (3.3V or 2.5)
operation with the added capability of interfacing to a 5V
signal environment.
The 74LCX112 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs
s 2.3V–3.6V VCC specifications provided
s 7.5 ns tPD max (VCC = 3.3V), 10 µA ICC max
s Power down high impedance inputs and outputs
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 2000V
Ordering Code:
Order Number Package Number
Package Description
74LCX112M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74LCX112SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX112MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
© 1999 Fairchild Semiconductor Corporation DS012424.prf
www.fairchildsemi.com

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74LCX112 equivalent
AC Loading and Waveforms Generic for LCX Family
FIGURE 1. AC Test Circuit
(CL includes probe and jig capacitance)
Test
tPLH, tPHL
tPZL, tPLZ
tPZH,tPHZ
Switch
Open
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output Low Enable and
Disable Times for Logic
Propagation Delay, Pulse Width and trec Waveforms
Setup Time, Hold TIme and Recovery TIme for Logic
3-STATE Output High Enable and
Disable TImes for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Pulse Characteristics; f=1MHz, tr=tf=3ns)
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH 0.3V
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH 0.15V
5 www.fairchildsemi.com


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Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 74LCX112 electronic component.


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