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PDF 74LCX00SJ Data sheet ( Hoja de datos )
| Número de pieza | 74LCX00SJ | |
| Descripción | Low Voltage Quad 2-Input NAND Gate | |
| Fabricantes | Fairchild Semiconductor | |
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December 2013
74LCX00
Low Voltage Quad 2-Input NAND Gate
with 5V Tolerant Inputs
Features
■ 5V tolerant inputs
■ 2.3V–3.6V VCC specifications provided
■ 5.2ns tPD max. (VCC = 3.3V), 10µA ICC max.
■ Power down high impedance inputs and outputs
■ ±24mA output drive (VCC = 3.0V)
■ Implements proprietary noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance:
– Human body model > 2000V
– Machine model > 200V
■ Leadless DQFN package
General Description
The LCX00 contains four 2-input NAND gates. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
The 74LCX00 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Information
Package
Order Number Number
Package Description
74LCX00M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX00SJ
74LCX00BQX(1)
M14D
MLP14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX00MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
www.fairchildsemi.com
1 page  
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
VCC (V)
3.3
2.5
3.3
2.5
Conditions
CL = 50pF, VIH = 3.3V, VIL = 0V
CL = 30pF, VIH = 2.5V, VIL = 0V
CL = 50pF, VIH = 3.3V, VIL = 0V
CL = 30pF, VIH = 2.5V, VIL = 0V
TA = 25°C
Typical
0.8
0.6
–0.8
–0.6
Unit
V
V
Capacitance
Symbol
CIN
COUT
CPD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = Open, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC, f = 10MHz
Typical
7
8
25
Units
pF
pF
pF
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
5
www.fairchildsemi.com
5 Page 
Physical Dimensions (Continued)
Figure 5. 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 74LCX00SJ.PDF ] | |
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