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PDF 74LS194A Data sheet ( Hoja de datos )
| Número de pieza | 74LS194A | |
| Descripción | LOW POWER SCHOTTKY | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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SN74LS194A
4-Bit Bidirectional
Universal Shift Register
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal
Shift Register. As a high speed multifunctional sequential building
block, it is useful in a wide variety of applications. It may be used in
serial-serial, shift left, shift right, serial-parallel, parallel-serial, and
parallel-parallel data register transfers. The LS194A is similar in
operation to the LS195A Universal Shift Register, with added features
of shift left without external connections and hold (do nothing) modes
of operation. It utilizes the Schottky diode clamped process to achieve
high speeds and is fully compatible with all ON Semiconductor TTL
families.
• Typical Shift Frequency of 36 MHz
• Asynchronous Master Reset
• Hold (Do Nothing) Mode
• Fully Synchronous Serial or Parallel Data Transfers
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 0.4
8.0
mA
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
Shipping
SN74LS194AN 16 Pin DIP 2000 Units/Box
SN74LS194AD
16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS194A/D
1 page  
SN74LS194A
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
ts
ts
th
trec
Parameter
Clock or MR Pulse Width
Mode Control Setup Time
Data Setup Time
Hold time, Any Input
Recovery Time
Limits
Min Typ Max
20
30
20
0
25
Unit
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME(ts) —is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
CLOCK
tPHL
OUTPUT
1/fmax
1.3 V
tW
1.3 V
1.3 V
tPLH
1.3 V
OTHER CONDITIONS: S1 = L, MR = H, S0 = H
Figure 1. Clock to Output Delays Clock Pulse
Width and fmax
MR
CLOCK
OUTPUT
1.3 V
tW
tPHL
1.3 V
trec
1.3 V
OTHER CONDITIONS: S0, S1 = H
OTHER CONDITIONS: PO = P1 = P2 = P3 = H
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
S0 (––– IS SHIFT LEFT)
S1
DSR DSL
P0 P1 P2 P3
th(L) = 0
CLOCK
OUTPUT*
ts(L)
1.3 V
ts(L)
th(L) = 0
ts(H)
th(H) = 0
1.3 V
1.3 V
ts(H)
th(H) = 0
OTHER CONDITIONS: MR = H
OTHER CONDITIONS: *DSR SET-UP TIME AFFECTS Q0 ONLY
OTHER CONDITIONS: DSL SET-UP TIME AFFECTS Q3 ONLY
Figure 3. Setup (ts) and Hold (th) Time for Serial Data
(DSR, DSL) and Parallel Data (P0, P1, P2, P3)
(STABLE TIME)
S0 S1
CLOCK
ts
th = 0
th = 0
1.3 V
1.3 V
ts
1.3 V
OTHER CONDITIONS: MR = H
Figure 4. Setup (ts) and Hold (th) Time for S Input
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74LS194A.PDF ] | |
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