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What is X1243V8?

This electronic component, produced by the manufacturer "Xicor", performs the same function as "Real Time Clock/Calendar/Alarm with EEPROM".


X1243V8 Datasheet PDF - Xicor

Part Number X1243V8
Description Real Time Clock/Calendar/Alarm with EEPROM
Manufacturers Xicor 
Logo Xicor Logo 


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16K
X1243
2-WireRTC
Real Time Clock/Calendar/Alarm with EEPROM
FEATURES
• 2 Alarms—Interrupt Output
—Settable on the Second, 10s of Seconds,
Minute, 10s of Minutes, Hour, Day, Month, or
Day of the Week
—Repeat alarm for time base generation
• 2 Wire Interface interoperable with I2C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant
• 2K bytes of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1µA Operating Current
—<3mA Active Current during Program
—<400µA Active Current during Data Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
—8-Lead SOIC Package, 8L TSSOP Package
DESCRIPTION
The X1243 is a Real Time Clock with clock/calendar
circuits and two alarms. The dual port clock and alarm
registers allow the clock to operate, without loss of
accuracy, even during read and write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
An alarm match of the RTC sets an interrupt flag and
activates an interrupt pin. An alternative alarm function
provides a pulsed interrupt for long time constant time-
bases.
The device offers a backup power input pin. This
Vback pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational
from 1.8 to 5.5 volts.
The X1243 provides a 2K byte EEPROM array, giving
a safe, secure memory for critical user and configura-
tion data. This memory is unaffected by complete fail-
ure of the main and backup supplies.
BLOCK DIAGRAM
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
IRQ
Control
Decode
Logic
8
Control
Registers
(EEPROM)
Status
Register
(SRAM)
Interrupt Enable
Alarm
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
9900-3003.1 4/1/99
1
Alarm
Compare
Alarm Regs
(EEPROM)
16K
EEPROM
Array
Characteristics subject to change without notice

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X1243V8 equivalent
X1243
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The Clock
Default values define 0=Sunday.
Clock/Calendar Registers (YR, MO, DT, HR, MN, SC)
These registers depict BCD representations of the time.
As such, SC (Seconds) and MN (Minutes) range from
00 to 59, HR (Hour) is 1 to 12 with an AM or PM indica-
tor (H21 bit) or 0 to 23 (with T24=1), DT (Date) is 1 to
31, MO (Month) is 1 to 12, YR (year) is 0 to 99.
24 Hour Time
If the T24 bit of the HR register is 1, the RTC will use a
24-hour format. If the T24 bit is 0, the RTC will use 12-
hour format and bit H21 will function as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
Standard Time with H21=0.
Leap Years
Leap years add the day February 29 and are defined as
those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible by
400. This means that the year 2000 is a leap year, the
year 2100 is not. The X1243 does not correct for the
leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the RTC area at
address 003FH. This is a volatile register only and is
used to control the WEL and RWEL write enable
latches, read an optional Low Voltage Sense bit, and
read the two alarm bits. This register is logically seper-
ated from both the array and the Clock/Control Regis-
ters (CCR).
Table 2. Status Register (SR)
Addr 7 6 5 4
003Fh BAT AL1 AL0 0
Default 0 0 0 0
32 1 0
0 RWEL WEL RTCF
00 0 0
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read only bit and is set/
reset by hardware.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 1 or alarm 2 match
the real time clock. If there is a match, the respective bit
is set to ‘1’. The falling edge of the last data bit in a SR
Read operation resets the flags. Note: Only the AL bits
that are set when an SR read starts will be reset. An
alarm bit that is set by an alarm occuring during an SR
read operation will remain set after the read operation
is complete.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both the
RWEL and WEL bits to be set in a specific sequence.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and mem-
ory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Status
Register. Once set, WEL remains set until either reset
to 0 (by writing a “0” to the WEL bit and zeroes to the
other bits of the Status Register) or until the part pow-
ers up again. Writes to WEL bit do not cause a non-vol-
atile write cycle, so the device is ready for the next
operation immediately after the stop condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is a
read only bit that is set by hardware when the device
powers up after having lost all power to the device. The
bit is set regardless of whether VCC or VBACK is applied
first. The loss of one or the other supplies does not
result in setting the RTCF bit. The first valid write to the
RTC (writing one byte is sufficient) resets the RTCF bit
to ‘0’.
Unused Bits:
These devices do not use bits 3 or 4, but must have a
zero in these bit positions. The Data Byte output during
a SR read will contain zeros in these bit locations.
5


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X1243V8The function is Real Time Clock/Calendar/Alarm with EEPROM. XicorXicor

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