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PDF UPD43256B Data sheet ( Hoja de datos )
| Número de pieza | UPD43256B | |
| Descripción | 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD43256B
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
Description
The µPD43256B is a high speed, low power, and 262, 144 bits (32,768 words by 8 bits) CMOS static RAM.
Battery backup is available (L, LL, A, and B versions). And A and B versions are wide voltage operations.
The µPD43256B is packed in 28-pin plastic DIP, 28-pin plastic SOP and 28-pin plastic TSOP (I).
Features
• 32,768 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Wide voltage range (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• 2 V data retention
• OE input for easy application
Part number
Access time
ns (MAX.)
µPD43256B-L
70, 85
µPD43256B-LL
70, 85
µPD43256B-A
85, 100Note 2, 120Note 2
µPD43256B-BNote 2 100, 120, 150
Operating
supply voltage
V
4.5 to 5.5
3.0 to 5.5
2.7 to 5.5
Operating
temperature
°C
0 to 70
Standby
supply current
µA (MAX.)
50
15
Data retention
supply currentNote 1
µA (MAX.)
3
2
Notes 1. TA ≤ 40 ˚C, VCC = 3 V
2. Access time : 85 ns (MAX.) (VCC = 4.5 to 5.5 V)
Version X and P
This data sheet can be applied to the version X and P. Each version is identified with its lot number. Letter X in
the fifth character position in a lot number signifies version X, letter P, version P.
D43256B
JAPAN
Lot number
The information in this document is subject to change without notice.
Document No. M10770EJ9V0DS00 (9th edition)
Date Published May 1997 N
Printed in Japan
The mark shows major revised points.
©
1990, 1993, 1994
1 page  
Block Diagram
A0
|
A14
I/O1
|
I/O8
µPD43256B
Memory cell array
262,144 bits
Input data
controller
Sense/Switch
Column decoder
Address buffer
Output data
controller
CS
OE
WE
VCC
GND
Truth Table
CS OE WE
H× ×
L HH
L×L
L LH
Mode
Not selected
Output disable
Write
Read
I/O
High impedance
DIN
DOUT
Supply current
ISB
ICCA
Remark ×: Don’t care
5
5 Page 
Read Cycle Timing Chart
Address (Input)
CS (Input)
tRC
tAA
tACS
tCLZ
OE (Input)
I/O (Output)
tOLZ
High impedance
tOE
µPD43256B
tOH
Data out
tCHZ
tOHZ
High impedance
Remark In read cycle, WE should be fixed to high level.
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet UPD43256B.PDF ] | |
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