UPD16873MC-6A4 Datasheet PDF - NEC
Part Number | UPD16873MC-6A4 | |
Description | MONOLITHIC 3-ASPECT SPINDLE MOTOR DRIVER | |
Manufacturers | NEC | |
Logo | ||
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MOS Integrated Circuit
µPD16873/A/B/C
MONOLITHIC 3-ASPECT SPINDLE MOTOR DRIVER
DESCRIPTION
µPD16873/A/B/C is 3 aspect spindle motor driver that composed by CMOS control circuit and MOS bridge output.
The consumption electric power can be substantially reduced to the screwdriver which used a conventional
Bipolar transistor by the adoption of 3 aspect all-wave PWM methods and making an output paragraph MOSFET.
FEATURES
• Low On resistance. (The summation of the on resistance of the upper and lower MOSFET) RON = 0.6 Ω (TYP.)
• Low consumption power for 3 aspects all-wave PWM drive method.
• Index pulse (FG pulse) output function built in.
• By the PWM-drive form and the IND pulse pattern, 4 kind, line-up
µPD16873
µPD16873A
µPD16873B
µPD16873C
PWM method
normal
normal
synchronous
synchronous
Pattern of IND pulse (at 12 pole motor)
3 phase composition output (18 pulses/turn)
1 phase output (6 pulses/turn)
1 phase output (6 pulses/turn)
3 phase composition output (18 pulses/turn)
• Built in STANDBY terminal and off the inner circuit at the time of the standby.
• Built in START/STOP terminal. Operating short brake works, when ST/SP terminal is off state.
• Supply voltage: 5 V drive
• Low consumption current: IDD = 3 mA (MAX.)
• Thermal shut down circuit (TSD) built in.
• Over current protection circuit built in. (Setting by outside resistance)
• Low voltage malfunction prevention circuit built in.
• Reverse turn prevention circuit built in.
• Hall bias switch built in. (synchronized STB signal.)
• Loading into 30-pin plastic TSSOP (300 mil).
ORDERING INFORMATION
Part number
µPD16873MC-6A4
µPD16873AMC-6A4
µPD16873BMC-6A4
µPD16873CMC-6A4
Function
normal-PWM/3 phase IND
normal-PWM/1 phase IND
synchronous-PWM/1 phase IND
synchronous-PWM/3 phase IND
Package
30-pin plastic TSSOP (7.62 mm (300))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13870EJ1V0DS00 (1st edition)
Date Published February 2000 N CP(K)
Printed in Japan
©
2000
|
|
BLOCK DIAGRAM
IND 1
STB 2
VM 3
VM 4
Q5
OUT2 5
Q6
RF 6
RF 7
OUT1 8
VM 9
VM 10
OUT0 11
RF 12
RF 13
Q3
Q4
Q1
Q2
ISEN 14
CL 15
+
−
100 mV
µPD16873/A/B/C
Phase
exciting
pulse
generation
circuit
Reverse
turn
detection
circuit
30 EC
29 ECR
UVLO
OSC
T. S. D
CMP2
+
−
CMP1
+
−
CMP0
+
−
28 VDD
27 CT
26 H2+
25 H2−
24 H1+
23 H1−
22 H0+
21 H0−
20 HB
19 GND
18 GND
17 ST/SP
16 NC
Caution Plural terminal (VM, RF, GND) is not only 1 terminal and connect all terminals.
Data Sheet S13870EJ1V0DS00
5
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Information | Total 16 Pages | |
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