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PDF UPD16823GS Data sheet ( Hoja de datos )
| Número de pieza | UPD16823GS | |
| Descripción | MONOLITHIC H BRIDGE DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16823
MONOLITHIC H BRIDGE DRIVER
DESCRIPTION
This IC is a monolithic H bridge driver employing a horizontal N-channel power MOS FET for its driver stage.
It is provided with forward/reverse and brake functions and is ideal as a driver circuit for a motor that winds or
rewinds the film in a camera, or a motor for moving a lens.
FEATURES
• High drive current IDR1 = 0.5 A (DC)
IDR2 = 1 A: at PW ≤ 200 ms, duty cycle ≤ 50%
IDR3 = 3 A: at PW ≤ 200 ms, single pulse
• 1.5ch H bridge circuits
• Low ON resistance (sum of ON resistance of top and bottom FETs)
RON = 0.6 Ω TYP. at IDR = 0.5 A
• Standby function that turns OFF charge pump circuit
• Low-voltage drive (2.5 V MIN.)
• Surface-mount mini-mold package: 20-pin plastic SOP (300 mil)
ORDERING INFORMATION
Part Number
µPD16823GS
Package
20-pin plastic SOP (300 mil)
BLOCK DIAGRAM
VDD
C1 C2
STBY
IN1
IN2
IN3
OSC
CIRCUIT
CONTROL
CIRCUIT
Pull-down
resistor:
50 kΩ
CHARGE
PUMP
CIRCUIT
LEVEL
SHIFT
CIRCUIT
C3
External capacitors C1 through C3: 10 nF
External capacitor C4:
1 to 10 µF
VM
LDMOS
H BRIDGE
CIRCUIT
OUT1
OUT2
OUT3
Motor 1
Motor 2
LGND
PGND
The information in this document is subject to change without notice.
Document No. S12721EJ2V0DS00 (2nd edition)
Date Published August 1997 N
Printed in Japan
©
1997
1 page  
Battery
DC-DC
converter
VM = 0.5 to 7.5 V
VDD = 3.0 to 6.0 V
C1 = C2 = C3 = 10 nF
C1 C2
C3
VDD
7
23
20 1
VG
19
VM
6
CPU
STBY 18
OSC
CIRCUIT
CHARGE PUMP CIRCUIT
IN1 10
IN2 8
IN3 9
CONTROL
CIRCUIT
Pull-down
resistor: 50 kΩ TYP.
µPD16823GS
LEVEL SHIFT
CIRCUIT
12
DGND
D MOS FET
H BRIDGE
CIRCUIT
(1.5 circuits)
14, 16
PGND
19
VM
C4Note
1 to 10 µF
15 OUT1
5 OUT2
17 OUT3
M
M
IN1 L
IN2 H
IN3 L
L
H
H
H
L
LH
H
1CH
1CH
1CH
2CH
2CH
Forward mode Reverse mode Brake mode Forward mode Reverse mode
2CH
Brake mode
Note It is recommended to connect an external
capacitor of 1 to 10 µF between VM and
GND to protect the gate of the D MOS FET
from voltage surge.
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet UPD16823GS.PDF ] | |
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