UPD16772N Datasheet PDF - NEC
Part Number | UPD16772N | |
Description | 480-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64-GRAY SCALES | |
Manufacturers | NEC | |
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There is a preview and UPD16772N download ( pdf file ) link at the bottom of this page. Total 20 Pages |
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MOS INTEGRATED CIRCUIT
µ PD16772
480-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µ PD16772 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors
by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the
output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line
inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit
whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a
clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to UXGA-standard TFT-LCD panels.
FEATURES
• CMOS level input (2.3 to 3.6 V)
• 480 outputs
• Input of 6 bits (gradation data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-
DAC)
• Output dynamic range : VSS2 + 0.1 V to VDD2 – 0.1 V
• High-speed data transfer : fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V)
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity inversion function (POL)
• Display data inversion function (POL21/22)
• Current consumption reduction function (LPC, Bcont)
• Logic power supply voltage (VDD1) : 2.3 to 3.6 V
• Driver power supply voltage (VDD2) : 8.5 V ± 0.5 V
ORDERING INFORMATION
Part Number
µ PD16772N-xxx
Package
TCP (TAB package)
Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our
sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14416EJ1V0DS00 (1st edition)
Date Published August 2000 NS CP (K)
Printed in Japan
The mark • shows major revised points.
©
1999, 2000
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µPD16772
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order.
Reverse this sequence to shut down (Simultaneous power application to VDD2 and V0 to V9 is
possible.).
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion
of a bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply
terminals (V0, V1, V2,....., V9) and VSS2.
Data Sheet S14416EJ1V0DS00
5
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Information | Total 20 Pages | |
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Download | [ UPD16772N.PDF Datasheet ] |
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